ADV8003 Hardware Manual
Rev. B, August 2013
272
The mapping between the I2S input signals to the Tx core and the HBR subpackets can be via the following controls:
•
subpkt0_l_src
•
subpkt0_r_src
•
subpkt1_l_src
•
subpkt1_r_src
•
subpkt2_l_src
•
subpkt2_r_src
•
subpkt3_l_src
•
subpkt3_r_src
Note:
When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8003, the fields listed
above are set to the respective default values. Since there is no standard for chip to chip HBR transfer, different settings may be required to
map the HBR stream input to the Tx core and a non ADI HDMI Rx device.
Refer to
for additional details on the HBR modes supported by the ADV8003.
papb_sync
, TX2 Main Map,
Address 0xF447[6]
This bit us used to synchronize the Pa and Pb syncwords with subpacket 0 for HBR audio.
Function
papb_sync
Description
0
No function
1
Synchronize Pa and Pb syncwords with subpacket 0
6.11.3.
N and CTS Parameters
The audio data carried across the HDMI link to the downstream sink, which is driven by a TMDS clock only, does not retain the original
audio sample clock. The task of recreating this clock at the sink is called Audio Clock Regeneration (ACR). There are varieties of ACR
methods that can be implemented in an HDMI sink, each with a different set of performance characteristics. The HDMI specification
does not attempt to define exactly how these mechanisms operate. It does, however, present a possible configuration and defines the data
items that the HDMI source shall supply to the HDMI sink in order to allow the HDMI sink to adequately regenerate the audio clock.
The HDMI specification also defines how that data shall be generated. In many video source devices, the audio and video clocks are
generated from a common clock (coherent clocks). In that situation, there exists a rational (integer divided by integer) relationship
between these two clocks. The ACR architecture can take advantage of this rational relationship and can also work in an environment
where there is no such relationship between these two clocks, that is, where the two clocks are truly asynchronous or where their
relationship is unknown.
Summary of Contents for ADV8003
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