ADV8003 Hardware Manual
Rev. B, August 2013
291
Function
arc_pins_oe_man
Description
0
Input
1
Output
arc_pins_oe_man_en
, IO Map,
Address 0x1ACB[7]
This bit is used to control the manual override for ARC outputs.
Function
arc_pins_oe_man_en
Description
0
Auto
1
Manual override
To increase the noise immunity of the ADV8003 ARC Rxs, it is recommended to enable the input hysteresis block on both blocks via
and
tx1_arc_bias_hyst_adj
, IO Map,
Address 0x1A88[1]
This bit is used to control the addition of hysteresis to the TX1 ARC.
Function
tx1_arc_bias_hyst_adj
Description
0
Normal
1
ADD hysteresis
tx2_arc_bias_hyst_adj
, IO Map,
Address 0x1A8A[1]
This bit is used to control the addition of hysteresis to the TX2 ARC.
Function
tx2_arc_bias_hyst_adj
Description
0
Normal
1
ADD hysteresis
6.15.
CHARGE INJECTION SETTINGS
The ADV8003 features adjustable charge injection settings to help adjust the HDMI signal rise and fall times to account for variations
between different hardware implementations e.g. different board layouts, board materials, the presence of ESD devices or common-mode
chokes, variations in connector type. Failure to adjust the charge injection settings may result in a system failing HDMI compliance
testing due to the HDMI signal rise and fall times being too slow or fast.
The clock charge injection controls are controlled by registers 0xECE9[7:0] and 0xECF7[7:6]. These bits incorporate a series of
proprietary enables and controls which enable and disable various charge injection paths. The data charge injection controls are controlled
by registers 0xECEC[7:0] and 0xECF7[5:4]. These bits incorporate a series of proprietary enables and controls which enable and disable
various charge injection paths.
Various charge injection options are covered in Table 71.
Table 71: Charge Injection Settings
Clock Charge
Injection
0xECE9[7:0]
0xECF7[7:6]
Data Charge
Injection
0xECEC[7:0]
0xECF7[5:4]
0
00000100
00
0
00000100
00
Summary of Contents for ADV8003
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