ADV8003 Hardware Manual
Rev. B, August 2013
351
edge_sensitive_int_raw
, IO,
Address 0xXX (Read Only)
This readback indicates the status of the edge sensitive interrupt. When set to 1, it indicates that an event has occured. Once set, this bit
remains high until the interrupt is cleared via edge_sensitive_int_clr.
Function
edge_sensitive_int_raw
Description
0
No event/condition occured
1
Event/condition occured
Level-senstivitive bit,
level_sensitive_int_raw
,
always represents the current status of whether or not a particular event or condition is
occurring e.g. if the part is receiving AVI InfoFrames. It is not a latched bit and never requires to be cleared.
Edge-sensitive bit,
edge_sensitive_int_raw
, indicates that a transient event or condition has occurred; it is latched and it needs to be
cleared. This approach is adopted for important events which have a transient nature e.g. if the part has received a new AVI Infoframe. If
edge_sensitive_int_raw
did not latch and returned to 0 some time after the event occurred, the user could miss the fact that the event or
condition occurred. Therefore, edge-sensitive raw bits do not truly represent the current status; instead, the represent the status of an edge
event that happened in the past. To clear a latched bit, the user must set the corresponding clear bit to 1.
provide a graphical example of what how edge and level sensitive interrups operate.
SAMPLING
CHANGE
DETECTION
(Rising and
Falling edge)
HOLD UNTIL
CLEARED
APPLY
MASK
OR
SAMPLING
CHANGE
DETECTION
(Rising edge)
HOLD UNTIL
CLEARED
APPLY
MASK
INT
Output
Internal
Status Flag
Internal
Pulse Flag
xxx_RAW
xxx_ST
xxx_CLR
xxx_MB1
yyy_CLR
yyy_MB1
yyy_RAW
yyy_ST
Interrupt path for level
sensitive Interrupts
Interrupt path for edge
sensitive Interrupts
Figure 134: Level and Edge-sensitive Raw, Status and Interrupt Generation
Summary of Contents for ADV8003
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