ADV8003 Hardware Manual
Rev. B, August 2013
68
It is possible to use the subaddresses auto-increment feature, which allows data to be accessed from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without
having to update all the registers.
Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with
normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period, the user
should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid
subaddress is issued by the user, the ADV8003 does not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress in auto increment mode, the following actions are taken:
•
In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse.
•
In write mode, the data for the invalid byte is not loaded into any subaddress register. A no acknowledge is issued by the
ADV8003 and the part returns to the idle condition.
S
1-7
8
9
9
9
P
Device
Address
1-8
9
Register
Address (MSBs)
Register
Address (LSBs)
Data
ACK
R/W
1-8
1-8
ACK
ACK
ACK
SDA
SCL
S
1-7
8
9
9
9
P
Device
Address
1-8
9
Register
Address (MSBs)
Register
Address (LSBs)
Data
ACK
R/W
1-8
1-8
ACK
ACK
ACK
S
1-7
8
9
9
9
P
Device
Address
1-8
9
Register
Address (MSBs)
Register
Address (LSBs)
Data
ACK
R/W
R/W
1-8
1-8
ACK
ACK
ACK
SDA
SCL
Figure 12: Bus Data Transfer
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(S)
Data
A/(S)
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(M)
Data
A/(M)
S
Device
Address
P
P
S = Start Bit
P = Stop Bit
A(S) = Acknowledge by Slave
A(M) = Acknowledge by Master
A(S) = Acknowledge by Slave
A(M) = Acknowledge by Master
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(S)
Data
A/(S)
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(M)
Data
A/(M)
S
Device
Address
P
P
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(S)
Data
A/(S)
S
Device
Address
A/(S)
Register
Address [MSBs]
Register
Address [LSBs]
A/(S)
Data
A/(S)
A/(M)
Data
A/(M)
S
Device
Address
P
P
S = Start Bit
P = Stop Bit
A(S) = Acknowledge by Slave
A(M) = Acknowledge by Master
A(S) = Acknowledge by Slave
A(M) = Acknowledge by Master
Figure 13: Read and Write Sequence
1.6.
CONFIGURING THE ADV8003
The ADV8003 requires a number of configuration settings for each mode of operation. To ensure the part is correctly configured, refer to
either the recommended settings configuration script (supplied with the ADV8003 evaluation software) or the reference software driver.
Failure to follow these recommended settings will result in the part not operating to its optimum performance.
Summary of Contents for ADV8003
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