ADV8003 Hardware Manual
Rev. B, August 2013
77
2.1.7.
Mode 6
Mode 6 should be used if:
•
Two separate upscaled resolutions are required
•
De-interlacing is not required
•
OSD is required on one resolution only (preferably the lower upscaled resolution output)
720p OSD
from
External FPGA
OSD
Blend
Build
OSD
Scale
OSD
Secondary
VSP
Output
Muxing
Mode 6
DDR2 Memory
Interface
(720p)
(480p)
(1080p)
(720p)
1080p
720p(OSD)
1080p
(720p)
(720p)
Primary
VSP
HDMI
Tx2
HDMI
Tx1
HD
Encoder
SD
Encoder
480p Video
from
Decoder
(720p)
Video
36-bit
Input
Port
Exosd
24-bit
Input
Port
Serial
Video
RX
Input
Muxing
Secondary:
Data
Formatting
& CSC
Primary:
Data
Formatting,
CSC & ACE
RX:
Data
Formatting
& CSC
Video
Muxing
720p OSD
from
External FPGA
OSD
Blend
Build
OSD
Scale
OSD
Secondary
VSP
Output
Muxing
Mode 6
DDR2 Memory
Interface
(720p)
(480p)
(1080p)
(720p)
1080p
720p(OSD)
1080p
(720p)
(720p)
Primary
VSP
HDMI
Tx2
HDMI
Tx1
HD
Encoder
SD
Encoder
480p Video
from
Decoder
(720p)
Video
36-bit
Input
Port
Exosd
24-bit
Input
Port
Serial
Video
RX
Input
Muxing
Secondary:
Data
Formatting
& CSC
Primary:
Data
Formatting,
CSC & ACE
RX:
Data
Formatting
& CSC
Video
Muxing
Figure 20: ADV8003 Mode 6 Configuration
Mode 6 places the OSD blend block after the SVSP. Both the PVSP block and SVSP work in parallel in this mode. As the OSD is only on
one data path, it will only be displayed at a single resolution. As shown in the example in
, the input to the SVSP must be a
progressive format. Therefore, this mode can only be used when the input is progressive.
that the same output formats can be generated in this mode. However, due to the change in location of the
OSD blend block, the OSD can only be generated on a single output resolution.
Note:
De-interlaced inputs can be input to the device in this mode. However, the SVSP can only accept progressive input formats.
Therefore, the SVSP would be excluded from the processing in this case as would the OSD blend.
Summary of Contents for ADV8003
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