UG-707
ADV8005 Hardware Reference Manual
The PVSP supports the following cadence types:
•
2:2
•
2:2:2:4
•
3:2
•
2:3:3:2:2
•
2:3:3:2
•
3:2:3:2:2
•
3:3
•
4:4
•
5:5
•
6:4
•
8:7
Each of these cadence types can be disabled by setting the corresponding bit in
to 1.
For conversion of 60 Hz interlaced and progressive input timing to 24 Hz progressive timing,
should be asserted.
For all other cases,
should be disabled when using 1 external DDR2 memory.
pvsp_frc_change_phase_en
, Primary VSP Map,
Address 0xE84E[4]
This bit is used to lock the phase change for cadence detection.
Function
pvsp_frc_change_phase_en
Description
0
Disable
1 (default)
Enable
di_fd_disabled_cadence[10:0]
, Primary VSP Map,
Address 0xE8FA[7:0]; Address 0xE8FB[7:5]
This signal is used to disable corresponding cadence detection.
Function
di_fd_disabled_cadence[10:0]
Description
0x000 (default)
Default
Table 24: Corresponding Bit for Each Cadence Type
Bit
Disabled Cadence
0xE8FB[5]
2:2
0xE8FB[6]
2:2:2:4
0xE8FB[7]
3:2
0xE8FA[0]
2:3:3:2:2
0xE8FA[1]
2:3:3:2
0xE8FA[2]
3:2:3:2:2
0xE8FA[3]
3:3
0xE8FA[4]
4:4
0xE8FA[5]
5:5
0xE8FA[6]
6:4
0xE8FA[7]
8:7
3.2.3.6.
CUE Correction
Color Upsampling Error (CUE) correction is implemented using a filter which removes the jagged edges caused by the artifacts introduced by
the incorrect upsampling of MPEG 2 video data in 4:2:0 format to the 4:2:2/4:4:4 formats supported by DVD players.
The CUE correction function can be enabled or disabled by
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