UG-707
ADV8005 Hardware Reference Manual
ttl_out_sel[2:0]
, IO Map,
Address 0x1A02[2:0]
This signal is used to select the video source for the TTL video output.
Function
ttl_out_sel[2:0]
Description
0x00 (default)
From Primary Input Channel
0x01
From Primary VSP
0x02
From PtoI Converter
0x03
From Internal OSD Blend 1
0x04
From Secondary VSP/PtoI Converter
0x05
From Secondary Input Channel
0x06
From RX Input
0x07
From Internal OSD Blend 2
osd_clk_drv_str[1:0]
, IO Map,
Address 0x1BA7[1:0]
This signal is used to control the drive strength for the video output clock signal.
Function
osd_clk_drv_str[1:0]
Description
00 (default)
Minimum
01
Medium low (x2)
10
Medium high (x3)
11
Maximum (x4)
osd_dout_drv_str[1:0]
, IO Map,
Address 0x1BA3[1:0]
This signal is used to control the drive strength for the video output data and sync signals.
Function
osd_dout_drv_str[1:0]
Description
00 (default)
Minimum
01
Medium low (x2)
10
Medium high (x3)
11
Maximum (x4)
2.2.2.4.
Treatment o f Unused TTL Inputs
allows the TTL pins to be powered down when unused, removing the need for external pulldowns on many unused I/O pins.
Note:
The TTL pins are powered down by default, each of these pins must be powered up to use them. Unused pins should be left powered down.
vid_clk_ie
, IO Map,
Address 0x1BC8[5]
This bit is used to control the input path enable for the VID CLK pin.
Function
vid_clk_ie
Description
0 (default)
input path disable
1
input path enable
clk_osd_ie
, IO Map,
Address 0x1BC8[4]
This bit is used to control the input path enable for the osd clk pin.
Function
clk_osd_ie
Description
0 (default)
input path disable
1
input path enable
pix_pins_ie[31:0]
, IO Map,
Address 0x1BC9[7:0]; Address 0x1BCA[7:0]; Address 0x1BCB[7:0]; Address 0x1BCC[7:0]
This bit is used to control the input path enable for the pixel pins.
Function
pix_pins_ie[31:0]
Description
0 (default)
input path disable
1
input path enable
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