ADV8005 Hardware Reference Manual
UG-707
2.2.5.1.
DDR2 Configuration
The controls described in this section are used to configure the
The first three bits configure the DDR2 memory interface for the external memory configuration. The
sets the memory size of
the attached memory or memories. For example, if using 256 Mb memory,
should be set to 0001. If using 2 Gb memory,
should be set to 0100.
The
and
must also be configured depending on whether there are single or multiple memories connected to the
. If
there is a single DDR2 memory,
and
should be set for a 32-bit word size and bursts of 8. If there are dual DDR2 memories,
and
should be set for a 64-bit word size and bursts of 4.
is configured for dual 512 Mb memories with a 64-bit word size and bursts of 4.
sdram_size[3:0]
, IO Map,
Address 0x1A5B[7:4]
This signal is used to specify the SDRAM size. All values other than those specified here are reserved.
Function
sdram_size[3:0]
Description
0001
individual SDRAM is 256Mbit
0010 (default)
individual SDRAM is 512Mbit
0011
individual SDRAM is 1Gbit
0100
individual SDRAM is 2Gbit
word_size[3:0]
, IO Map,
Address 0x1A5C[7:4]
This signal is used to specify the word size on the user interface. The data width to the SDRAM is half of this value. All other values are
reserved
Function
word_size[3:0]
Description
0010
32 bits
0011 (default)
64 bits
burst_length[2:0]
, IO Map,
Address 0x1A5D[1:0]; Address 0x1A5E[7]
This signal is used to indicate the burst length of the read/write transaction.
Function
burst_length[2:0]
Description
010 (default)
Burst of 4
011
Burst of 8.
sets the direction for several of the pins on the DDR2 memory interface. By default, these pins are set to input. However, when set
to 1, this bit enables these pins to be outputs. Likewise, when
is set to 1, the DDR2 clock pin becomes an output.
rw_ctrl_oe
, IO Map,
Address 0x1AA8[7]
This bit is used to control the output enable for external memory read/write signals (ras, cas, clock, address…).
Function
rw_ctrl_oe
Description
0 (default)
Input
1
Output
ddr2_ck_oe
, IO Map,
Address 0x1AA8[6]
This bit is used to control the output enable for external memory clock signal.
Function
ddr2_ck_oe
Description
0 (default)
Input
1
Output
The PLL clock generator for the DDR2 memory interface can be set to a user defined frequency over the range of 200 to 250MHz by setting the
and the
2
C controls.
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