ADV8005 Hardware Reference Manual
UG-707
LRCLK
SCLK
DATA
LEFT
RIGHT
LSB
MSB
MSB
LSB
16 Clock Slots
16 Clock Slots
Figure 104: Timing for I2S Stream in Left or Right-Justified and 32-bit Modes
6.11.3.2.
SPDIF Audio
The
can receive two channel LPCM or encoded multichannel audio up to a 192 kHz sampling rate via the SPDIF input interface. The
detected sampling frequency for the SPDIF input stream can be read via the
field.
It is possible to set the sampling audio sampling frequency of the input SPDIF stream. This is done by setting
to 1.
When
is set to 1, the sampling frequency used to determine the pixel repetition factor (refer to
Section 6.11.1
) is not
extracted from the input SPDIF stream and must be programmed in the
field. Note that the sampling frequency that is used in the
Audio Sample packets sent to the downstream sink can be read from the
The
is capable of accepting SPDIF with or without an audio master clock input to through the input pin MCLK. When the
does not receive an audio master clock, the
uses the bit clock input via the SCLK pin to internally generate an audio master clock and
determine the CTS value.
spdif_sf[3:0]
, TX2 Main Map,
Address 0xF404[7:4] (Read Only)
This signal is used to readback the audio sampling frequency from the SPDIF channel.
Function
spdif_sf[3:0]
Description
0000 (default)
44.1kHz
0001
NA
0010
48 kHz
0011
32kHz
0100
NA
0101
NA
0110
NA
0111
NA
1000
88.2kHz
1001
NA
1010
96kHz
1011
NA
1100
176.4kHz
1101
NA
1110
192kHz
1111
NA
6.11.3.3.
DSD Audio
uses 1-bit Audio Sample packets to transmit DSD audio data across the HDMI link to the downstream sink. The
supports up to six channels of DSD data which can be input onto six data lines clocked by the signal input to DSD_CLK.
The
can be configured to receive a DSD stream by setting
to 0b010. The mode of the DSD stream input to the
field. The audio sampling frequency must be set via the
field. Note the DSD clock
input to SCLK has a frequency that is 64 times the audio sampling frequency programmed in the
field.
Refer to
for additional details on the DSD modes supported by the
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