ADV8005 Hardware Reference Manual
UG-707
Table 85: Serial Video Rx Edge Sensitive Interrupts
Interrupt
Mode of Operation
Description
rx_vs_inf_cks_err_
edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if there was an error with the vendor specific InfoFrame
rx_ms_inf_cks_err
_edge_ raw/st/mb2/clr
Edge sensitive
Used to indicate if there was an error with the MPEG source InfoFrame
rx_spd_inf_cks_er
r_edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if there was an error with a SPD InfoFrame
rx_avi_inf_cks_err
_edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if there was an error with the AVI InfoFrame
rx_deepcolor_chn
g_edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if the incoming video is deep color. The exact mode
can be determined by reading the DEEP_COLOR_MODE register
rx_tmds_clk_chng
_edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if the incoming TMDS clock has changed frequency
rx_pkt_err_edge_ raw/st/mb2/clr
Edge sensitive
Used to indicate if there was an error with any HDMI packet
rx_gamut_mdata_
pckt_edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if a gamut metadata packet was detected
rx_isrc2_pckt_edg
eraw/st/mb2/clr
Edge sensitive
Used to indicate if an ISRC2 packet was detected
rx_isrc1_pckt_edg
eraw/st/mb2/clr
Edge sensitive
Used to indicate if an ISRC1 packet was detected
rx_vs_info_frm_e
dge_raw/st/mb2/clr
Edge sensitive
Used to indicate if a vendor specific InfoFrame was detected
rx_ms_info_frm_e
dge_raw/st/mb2/clr
Edge sensitive
Used to indicate if an MPEG source InfoFrame was detected
rx_spd_info_frm_
edge_raw/st/mb2/clr
Edge sensitive
Used to indicate if a source product descriptor InfoFrame was detected
rx_avi_info_frm_e
dge_raw/st/mb2/clr
Edge sensitive
Used to indicate if an AVI InfoFrame was detected
8.2.2.1.
Multiple Interrupt Events
If an interrupt event occurs, and then a second interrupt event occurs before the system controller has cleared or masked the first interrupt
event, the
does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits as more
than one may be active.
8.2.3.
Serial Video Interrupts Validity Checking Process
All Serial Video interrupts have a set of conditions that must be taken into account for validation in the system firmware. When the
alerts the system controller with a Serial Video interrupt, the host must check that the following validity conditions for that interrupt are met
before processing that interrupt. This is valid for all the interrupts described above.
•
is configured in HMDI mode
•
rx_tmds_clk_det_raw
is set to 1 if the Serial Video Rx input is being used
•
rx_tmdspll_lck_raw
bit is set to 1
8.3.
VSP AND OSD SECTION
This section describes the interrupts provided by the
OSD and VSP section. These interrupts are not accessed through the I2C
interface as the interrupts for the Serial Video Rx and HDMI Tx are; these interrupts are accessed through the SPI interface. These interrupts
are not documented in detail as they are handled transparently to the user by the
Blimp OSD
software tool. Interrupts from this section are
output on the INT0 pin for use by the system microcontroller.
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