UG-707
ADV8005 Hardware Reference Manual
2.2.2.1.
Video TTL Input
The video TTL input pins are defined as follows:
•
P[47:0]
•
HS
•
VS
•
DE
•
PCLK
The video TTL input pins can be connected to either the primary input channel (refer to Section
) or the secondary input channel (refer
to
Section
2.2.2.2.
EXOSD TTL Input
The EXOSD TTL input pins are defined as follows:
•
OSD_IN[23:16]
•
OSD_IN[15]/VBI_SCK
•
OSD_IN[14]/VBI_MOSI
•
OSD_IN[13]/VBI_SCK
•
OSD_IN[12:0]
•
OSD_HS
•
OSD_VS
•
OSD_DE
•
OSD_CLK
The EXOSD TTL input pins can be connected to either the primary input channel (refer to
Section
or the secondary input channel (refer
to
Section
2.2.2.3.
TTL Output
includes a TTL output port, The external OSD TTL input pins (OSD_IN[23:0]) and 12 of the TTL input pins (P35:24) can
function as TTL output pins (refer to
and
. If all 36 TTL pins are used as outputs, this leaves only 24 pins for TTL inputs.
describes the different pinout options available for the TTL input and output buses. HS, VS, DE and the TTL clock are output on
the following pins:
•
OSD_IN[23:0]
•
P[35:24]
•
OSD_HS
•
OSD_VS
•
OSD_DE
•
OSD_CLK
The video data can be output at pixel frequencies up to 162 MHz. Only single data rate video is supported on the TTL output bus – it is not
possible to clock video out on the rising and falling edge of the TTL output clock.
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