UG-707
ADV8005 Hardware Reference Manual
Figure 38: DDR2 PLL Architecture
shows the block diagram of the PLL with the relevant I
2
C controls. The formula used to determine the frequency of the DDR2 memory
interface clock is given in
1
_
_
)
_
_
)(
(
_
2
+
≡
div
pre
plldll
div
sel
plldll
F
F
xtal_clk
clk
ddr
Equation 3: DDR2 Memory Interface Clock Frequency
The DDR2 clock frequency must not be changed during operation and should only be set prior to initialization of the memory interface.
plldll_sel_div[5:0]
, IO Map,
Address 0x1AA2[5:0]
This signal is used to control the DDR2 PLL loop divider. The DDR2 clock frequency is given by: fxtal * i2c_plldll_sel_div /
i2c_plldll_pre_div.
plldll_pre_div[1:0]
, IO Map,
Address 0x1AA3[3:2]
This signal is used to control the DDR2 PLL pre divider.
2.2.5.2.
DDR2 Bandwidth and Memory Selection
can be configured to work with one or two (default) DDR2 memories. Using a single DDR2 memory limits
the amount of functionality. Different capabilities are possible with different memory sizes. An outline of expected limitations are outlined in
Table 6: Indication of
Capabilities with One DDR2 Memory
Features
FRC
Motion
Adaptive De-
interlacing
Random Noise
Reduction
OSD
Dual Output (ADV8005-8A/8N/8C
only)
SD input
Supported
Supported
Supported
Total area of all OSD
regions (on screen at
same time) must be <
2 * 720 * 480 pixels.
(Entire OSD can be up-
scaled to desired
output resolution)
Supported
HD input
(720p)
Supported
N/A
Not supported
Supported
HD input
(1080i)
Supported
Intra-field
interpolation
not supported
Not supported
Supported
HD input
(1080p)
Not supported
- VSP_3D works
in bypass
mode
N/A
Not supported
Support only for:
TX1 ->1080p; TX2 ->
480p/720p/1080p, as VSP_3D
works in bypass mode
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