UG-901
EVAL-AD7175-8SDZ User Guide
Rev. 0 | Page 4 of 10
EVALUATION BOARD HARDWARE
DEVICE DESCRIPTION
The
is a highly accurate, high resolution, multiplexed,
8-/16-channel (full/pseudo differential) Σ-Δ ADC. The
has a maximum channel-to-channel scan rate of 50 kSPS (20 µs)
for fully settled data The output data rates range from 5 SPS to
250 kSPS. The device includes integrated analog input and
reference buffers, an integrated precision 2.5 V reference, and
an integrated oscillator.
HARDWARE LINK OPTIONS
See Table 1 for the default link options. By default, the board is
configured to operate from the supplied 9 V ac-to-dc adapter
connected to Connector J4. The 5 V supply required for the
comes from the on-board low dropout regulator
(LDO). The
, with a 5 V fixed output voltage, receives
its input voltage from J2 or J4 (depending on the position of LK2)
and generates a 5 V output.
Table 1. Default Link and Solder Link Options
Link
Default Option Description
LK1
A
Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place this
link in Position A if using 5 V AVDD1, or Position B if using 2.5 V AVDD1.
LK2
B
Selects the external power supply from Connector J3 (Position A), or J4 (Position B).
LK5 to LK20
Inserted
Inserting these links sets up the on-board noise test. In this mode, all inputs short to the common voltage
via SL11.
SL0
A
Routes A0 to one of the following:
Position A: AIN0/REF2− pin on the
Position B: Buffer U6
Position C: U7 for use with a single-ended to differential driver circuit
Position D: J15-1
SL1
A
Routes A1 to one of the following:
Position A: AIN1/REF2+ pin on the
Position B: Buffer U6
Position C: U7 for use with a single-ended to differential driver circuit
Position D: J15-7
SL2
A
Routes A2 to one of the following:
Position A: AIN2 pin on the
Position B: Buffer U10
Position C: U9 for use with a single-ended to differential driver circuit
SL3
A
Routes A3 to one of the following:
Position A: AIN3 pin on the
Position B: Buffer U10
Position C: U9 for use with a single-ended to differential driver circuit
SL4
A
Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets the
AVDD2 voltage to the 3.3 V supply from the
3.3 V regulator (U11).
SL5
B
Selects between an external or on-board IOVDD source. Supplies IOVDD from the
3.3 V
regulator (U11) (default). The evaluation board operates with a 3.3 V logic.
SL6
Removed
Position A connects Crystal Y1 as an external MCLK clock source. Position B connects the MCLK SMA/SMB
connector for use as a clock input or an ADC internal clock output.
SL7
A
Selects between an external or on-board AVDD1 source. Supplies AVDD1 from the
5 V regulator
(U8) (default).
SL8 to SL9
A
Selects between a 5 V and 2.5 V LDO supply for AVDD1. Supplies AVDD1 with 5 V (default).
SL10
A
Selects the voltage applied to the AVDD1 pin. Operates using the supply set up by Link SL8 to Link SL9
(default). When inserted in Position B, sets the AVDD1 voltage to the 3.3 V supply from the
3.3 V
regulator.
SL11
A
Selects the voltage applied to analog input during on-board noise test (LK5 to LK20 inserted). Position A
connects to the
REFOUT pin. Position B connects to GND. Position C connects to AVSS.
SL12 to SL15 Inserted
Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.
