HSC-ADC-EVALC
Rev. 0 | Page 8 of 32
THEORY OF OPERATION
The HSC-ADC-EVALC evaluation platform is based around
the Virtex-4 FPGA (XC4VFX20-10FFG672C) from Xilinx®,
which can be programmed through VisualAnalog to operate
with a variety of data converters. Another key component, the
Cypress USB device (U3), communicates with a host PC and
provides the SPI interface used for configuration.
CONFIGURATION
Some converter devices require programming for mode or
feature selection, which the SPI controller accomplishes using
SPI-accessible register maps. U3 drives the 4-wire SPI (SCLK,
SDI, SDO, CSB
1
) signals to the converter board via connector
(J1). For more information on serial port interface (SPI) func-
tions, consult the user manual titled
Interfacing to High Speed
ADCs via SPI
at
www.analog.com/FIFO
.
The SPI interface designed on the Cypress IC can communicate
with up to five different SPI-enabled devices including the
FPGA. The CLK and SDI/SDO data lines are common to all SPI
devices. The desired SPI-enabled device is selected for control
by using one of the five active low chip select (CS) pins. This
functionality is controlled by selecting a SPI channel in the SPI
Controller software.
At power-up, VisualAnalog attempts to autodetect the converter
that is attached to the ADC capture board using the SPI
interface. If a recognized device is found, VisualAnalog selects
the appropriate FPGA configuration; otherwise, the user is
prompted to make the device selection. In either case,
VisualAnalog then programs the FPGA using the SPI interface
of U3. The configurations typically program a FIFO data capture
function within the FPGA.
INPUT CIRCUITRY
The parallel data input pins of the FPGA, which interface to the
converter, are configurable. They can operate with 1.8 V, 2.5 V,
or 3.3 V logic levels and can accept LVDS or CMOS inputs.
Each channel of the ADC capture board requires a clock signal
to capture data. These clock signals are normally provided by
the attached ADC evaluation board and are passed along with
the data through one or more pins on Connector J2 and/or
Connector J3. Refer to the HSC-ADC-EVALC I/O connector
pin mappings shown in Figure 21 and Figure 22.
DATA CAPTURE
The process of filling the FIFO and reading the data back
requires several steps.
1.
VisualAnalog initiates the FIFO fill process by resetting
the FIFOs.
2.
The 48 MHz USB read clock (RCLK) is then suspended to
ensure that it does not add noise to the ADC input.
3.
VisualAnalog waits approximately 30 ms to allow for data
capture before beginning the readback process. This wait
time is an adjustable parameter in VisualAnalog.
4.
VisualAnalog reads the data from the FIFO through the
USB interface to the PC.
CODE DESCRIPTION
FPGA configuration files are provided by ADI for all ADCs
supported by the HSC-ADC-EVALC evaluation platform.
These files are designed and tested to facilitate quick
performance evaluations of Analog Devices data converters. No
additional FPGA programming is required from the user for
typical operation.
FPGA CONFIGURATION AND CUSTOMIZATION
Users can manually customize or update the FPGA code
through a JTAG connector (J10) provided on the ADC capture
board, as shown in Figure 17. However, Analog Devices
provides no support or guarantee of performance if the
provided code is customized by the user.
The HSC-ADC-EVALC hardware platform may contain addi-
tional circuit functions to support future developments and
capabilities. These functions are not supported beyond the
scope of this data sheet and the Analog Devices supplied data-
capture FPGA routines at this time.
Additional FPGA programming support may be available
through the user’s local Xilinx representative or distributor.
1
Note that CSB1 is the default CSB line used.
