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dc1416fa

DEMO MANUAL DC1416

DESCRIPTION

LT1222 and LT1793 

Low Noise 

Transimpedance Amplifier

Demonstration circuit 1416 is a low noise transimpedance 

amplifier. It utilizes the low voltage noise 

LT

®

1222

 op amp, 

and the low current noise 

LT1793

 op amp, along with the 

discrete NXP JFET BF862

1

 or equivalent, allowing the user 

to take advantage of each component’s particular opti-

PERFORMANCE SUMMARY

mization. These components are arranged with jumpers 

allowing various composite configurations. A socketed 

photodiode, OSRAM SFH213, is also provided. 

Design files for this circuit board are available at  

http://www.linear.com/demo/DC1416

Specifications are at T

A

 = 25°C, V

S

 = ±12V

SYMBOL

PARAMETER

CONDITIONS

TYP

UNITS

V

S

Supply Voltage 

±12

V

A

Z

TIA Gain 

1M

Ω

V

OS

Input Offset Voltage

LT1793 (V

OS

 + I

BIAS

 • 10M)

300

µV

dV

OS

 /dT

Input Offset Voltage Drift

LT1793 (dV

OS

/dT +dI

BIAS

/dT • 10M)

10

µV/C

I

BIAS

Input Bias Current

BF862

1

6

pA

en

Input Voltage Noise Density

f = 100kHz, JFET In Gain Configuration

1

nV/√

Hz

en

Input Voltage Noise Density

f = 100kHz, Source Follower Configuration

3

nV/√

Hz

C

IN

Input Capacitance

f = 10kHz, Source Follower Configuration

2

pF

GBW

Gain Bandwidth Product

JP In (C

COMP

 = 49pF) 

70

MHz

GBW

Gain Bandwidth Product

JP Out (C

COMP

 = 10pF) 

190

MHz

GBW

Gain Bandwidth Product

JP Out, C7 Removed (C

COMP 

= 0pF)

500

MHz

BW

–3dB Bandwidth

With SFH213, 1MΩ Gain, JP7 Out

2

MHz

V

OUT

Output Voltage Swing

Cathode Input, Integrator In

0 to 10

V

V

OUT

Output Voltage Swing

Cathode Input, Integrator Out

–0.4 to –10

V

V

OUT

Output Voltage Swing

Anode Input, Integrator In

0 to –10

V

V

OUT

Output Voltage Swing

Anode Input, Integrator Out

–0.4 to –10

V

I

CC

Supply Current 

V

S

 = ±12V

17

mA

I

BIAS

Input Bias Current

BF862

1

6

pA

PSRR

Power Supply Rejection Ratio

±5V to ±15V, Integrator In

95

dB

Note 1)

 BF862 has been obsoleted as of 2017. On-Semi 2SK932-22 has been substituted, with practically identical performance.

All registered trademarks and trademarks are the property of their respective owners.

Downloaded from

Arrow.com.

Summary of Contents for LT1222

Page 1: ...1793 BF8621 6 pA en Input Voltage Noise Density f 100kHz JFET In Gain Configuration 1 nV Hz en Input Voltage Noise Density f 100kHz Source Follower Configuration 3 nV Hz CIN Input Capacitance f 10kHz Source Follower Configuration 2 pF GBW Gain Bandwidth Product JP In CCOMP 49pF 70 MHz GBW Gain Bandwidth Product JP Out CCOMP 10pF 190 MHz GBW Gain Bandwidth Product JP Out C7 Removed CCOMP 0pF 500 MH...

Page 2: ...w the procedure below 1 With power off connect the 12V 12V and Com leads from the power supply to the V V and GND terminals of the demo circuit as shown in Figure 1 2 With power off connect the VOUT of the demo circuit to an oscilloscope or DMM You can use either the gold SMA connector or the turrets provided on board or both Set a high range such as 2V DIV on the oscil loscope or VDC on the DMM 3...

Page 3: ...1x3 JFET Drain 1 2 1 2 2 3 2 3 JP2 2x3 JFET Source 1 2 1 2 5 6 3 4 JP3 1x3 LT1222 Input 1 2 1 2 2 3 2 3 JP4 1x3 Photodiode Bias 1 2 1 2 1 2 1 2 JP5 1x3 Integrator Output 1 2 Out 2 3 Out JP6 1x3 Integrator Input 1 2 2 3 1 2 2 3 JP7 1x2 LT1222 Compensation Out Out In In JP8 1x2 LT1222 Input Out In Out Out Figure 1 Proper Supply Connections Board Is Shown for Source Follower with Integrator In JP1 th...

Page 4: ...ve Input Offset Voltage Is One JFET VGS About 400mV The Source Follower Configuration Is the Simplest and Most Versatile but the JFET In Gain Configuration Offers the Highest Achievable Gain Bandwidth Product and the Lowest Voltage Noise Output Noise at Low and Medium Frequencies 10kHz to 100kHz Is 130nV Hz Dominated Entirely by the Feedback Resistor Figure 3 The Two Basic Types of JFET Configurat...

Page 5: ...om its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices SCHEMATIC DIAGRAM 5 5 4 4 3 3 2 2 1 1 D D C C B B A A TECHNOLOGY GLEN B TECHNOLOGY GLEN B TECHNOLOGY GLEN B JP8 JP8 J1 J1 JP6 JP6 JP7 JP7 Figure 4 DC1416 Demo Circuit Schematic Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 6: ...y for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board inc...

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