ezTrainer
FGPAs made EAZY
User Manual
All Rights Reserved
Anaya Tech Systems Pvt Ltd
5.3 SDRAM INTERFACE
A 16-bit SDRAM of 128 Mbits is connected to the FPGA pins as shown in the table below. See datasheet of the
SDRAM at www.issi.com.
SPI_CS
55
1
SPI_DI
87
2
Table 3:
Signal Names
FPGA Pin
SDRAM pin
D0
25
2
D1
24
4
D2
23
5
D3
22
7
D4
19
8
D5
18
10
D6
16
11
D7
15
13
D8
12
42
D9
11
44
D10
9
45
D11
8
47
D12
5
48
D13
4
50
D14
3
51
D15
2
53
A0
69
23
A1
68
24
A2
65
25
A3
64
26
A4
63
29
A5
62
30
A6
50
31
A7
49
32
A8
48
33
A9
47
34
A10
45
22
Table 2:
Signal Names
FPGA Pin
M25P80 pin
