118
Performs a self test of the instrument data memory. Returns 0 if it is successful or
1 if the test fails.
*CLS
Clears the Status Byte summary register and event registers. Does not clear the
Enable registers.
*OPC
Sets the operation complete bit (bit 0) in the Standard Event register after a
command is completed successfully.
*OPC?
Returns an ASCII “1” after the command is executed.
*WAI
After the command is executed, it prevents the instrument from executing any
further query or commands until the no-operation-pending flag is TRUE.
*ESR?
Queries the power-on status clear setting. Returns 0 or 1.
*ESE <
value>
Standard Event enable register controls which bits will be logically ORed together
to generate the Event Summary bit 5 (ESB) within the Status Byte.
*ESE?
Queries the Standard Event enable register. Returns the decimal value of the
binary-weighted sum of bits.
*STB?
Read the Status Byte. Returns the decimal value of the binary-weighted sum of
bits.
*SRE <
value
>
Service Request enable register controls which bits from the Status Byte should
be used to generate a service request when the bit value = 1.
*SRE?
Queries the Service Request enable register. Returns the decimal value of
binary-weighted sum of bits.
*PSC {1|0}
Sets the power-on status clear bit. When set to 1 the Standard Event Enable
register and Status Byte Enable registers will be cleared when power is turned
ON. 0 setting indicates the Enable registers will be loaded with Enable register
Summary of Contents for 310XAC
Page 13: ...13 320XAC 340XAC...
Page 116: ...116 1 Test Complete OK WAI Wait for next command...
