B1.86
Instruction Fault Address Register
The IFAR characteristics are:
Purpose
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort
exception.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
IFAR(S)
-
-
-
RW -
-
RW
IFAR(NS) -
-
RW
-
RW RW
-
Configurations
IFAR (NS) is architecturally mapped to AArch64 register FAR_EL1[63:32]. See
.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
IFAR (S) is architecturally mapped to AArch32 register HIFAR. See
IFAR (S) is architecturally mapped to AArch64 register FAR_EL2[63:32]. See
.
Attributes
IFAR is a 32-bit register.
31
0
VA of faulting address of synchronous Prefetch Abort exception
Figure B1-41 IFAR bit assignments
VA, [31:0]
The Virtual Address of faulting address of synchronous Prefetch Abort exception.
To access the IFAR:
MRC p15, 0, <Rt>, c6, c0, 2; Read IFAR into Rt
MCR p15, 0, <Rt>, c6, c0, 2; Write Rt to IFAR
B1 AArch32 system registers
B1.86 Instruction Fault Address Register
100236_0100_00_en
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B1-293
Non-Confidential
Summary of Contents for Cortex-A35
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