C10.2
Performance Monitors Control Register
The PMCR characteristics are:
Purpose
Provides details of the Performance Monitors implementation, including the number of counters
implemented, and configures and controls the counters.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config Config RW
RW RW RW
RW
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations
PMCR is architecturally mapped to AArch64 PMCR_EL0 register. See
Monitors Control Register, EL0
PMCR[6:0] is architecturally mapped to external PMCR_EL0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
PMCR is a 32-bit register.
E
31
24 23
16 15
11 10
6 5 4 3 2 1 0
IMP
IDCODE
N
RES
0
DP X D C P
LC
7
Figure C10-1 PMCR bit assignments
IMP, [31:24]
Implementer code:
0x41
Arm.
This is a read-only field.
IDCODE, [23:16]
Identification code:
0x0A
Cortex
‑
A35.
This is a read-only field.
N, [15:11]
Number of event counters.
0b00110
Six counters.
[10:7]
Reserved,
RES0
.
LC, [6]
C10 PMU registers
C10.2 Performance Monitors Control Register
100236_0100_00_en
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-692
Non-Confidential
Summary of Contents for Cortex-A35
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