ARM Cortex-M0, Technical Reference Manual

Page 1: ...Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C ID112415 Cortex M0 Revision r0p0 Technical Reference Manual ...

Page 2: ...ever all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use ...

Page 3: ...ARM DDI 0432C Copyright 2009 ARM Limited All rights reserved iii ID112415 Non Confidential Web Address http www arm com ...

Page 4: ...iv Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 5: ... 2 Features 1 3 1 3 Interfaces 1 4 1 4 Configurable options 1 5 1 5 Product documentation design flow and architecture 1 6 1 6 Product revisions 1 9 Chapter 2 Functional Description 2 1 About the functions 2 2 2 2 Interfaces 2 4 Chapter 3 Programmers Model 3 1 About the programmers model 3 2 3 2 Modes of operation and execution 3 3 3 3 Instruction set summary 3 4 3 4 Memory model 3 9 3 5 Processor...

Page 6: ...xceptions 3 12 Chapter 4 System Control 4 1 About system control 4 2 4 2 System control register summary 4 3 Chapter 5 Nested Vectored Interrupt Controller 5 1 About the NVIC 5 2 5 2 NVIC register summary 5 3 Chapter 6 Debug 6 1 About debug 6 2 6 2 Debug register summary 6 9 Appendix A Revisions Glossary ...

Page 7: ...trol registers 4 3 Table 4 2 CPUID bit register assignments 4 4 Table 5 1 NVIC registers 5 3 Table 6 1 Cortex M0 ROM table identification values 6 4 Table 6 2 Cortex M0 ROM table components 6 4 Table 6 3 SCS identification values 6 5 Table 6 4 DWT identification values 6 6 Table 6 5 BPU identification registers 6 7 Table 6 6 Debug registers summary 6 9 Table 6 7 BPU register summary 6 9 Table 6 8 ...

Page 8: ...List of Tables viii Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 9: ...M Limited All rights reserved ix ID112415 Non Confidential List of Figures Cortex M0 Technical Reference Manual Figure 2 1 Functional block diagram 2 2 Figure 4 1 CPUID bit register assignments 4 4 Figure 6 1 CoreSight discovery 6 3 ...

Page 10: ...List of Figures x Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 11: ...t 2009 ARM Limited All rights reserved xi ID112415 Non Confidential Preface This preface introduces the Cortex M0 Technical Reference Manual It contains the following sections About this book on page xii Feedback on page xv ...

Page 12: ...ook is organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the processor and its features Chapter 2 Functional Description Read this chapter for a functional overview of the processor and its components Chapter 3 Programmers Model Read this chapter for an overview of the processor register set modes of operation and other information for programmin...

Page 13: ... in descriptive lists where appropriate monospace Denotes text that you can enter at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option You can enter the underlined text instead of the full command or option name monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specifi...

Page 14: ...on can include a Debug Access Port DAP This DAP is defined in v5 1 of the ARM Debug interface specification or in the errata document to Issue A of the ARM Debug Interface v5 Architecture Specification Application Binary Interface for the ARM Architecture The Base Standard IHI0036 Cortex M0 Integration and Implementation Manual ARM DII 0238 Cortex M0 User Guide Reference Material ARM DUI 0467A Oth...

Page 15: ...ntact your supplier giving The product name The product revision or version An explanation with as much information as you can provide Include symptoms if appropriate Feedback on this manual If you have any comments on this manual send an email to errata arm com Give the title the number ARM DDI 0432C the page numbers to which your comments apply a concise explanation of your comments ARM also wel...

Page 16: ...Preface xvi Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 17: ...uction This chapter introduces the Cortex M0 processor and its features It contains the following sections About the processor on page 1 2 Features on page 1 3 Interfaces on page 1 4 Configurable options on page 1 5 Product documentation design flow and architecture on page 1 6 Product revisions on page 1 9 ...

Page 18: ...ved ARM DDI 0432C Non Confidential ID112415 1 1 About the processor The Cortex M0 processor is a very low gate count highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized processor ...

Page 19: ...ith 32 bit performance power control optimization of system components integrated sleep modes for low power consumption fast code execution permits slower processor clock or increases sleep mode time hardware multiplier deterministic high performance interrupt handling for time critical applications Serial Wire Debug reduces the number of pins required for debugging For information about Cortex M0...

Page 20: ...opyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 1 3 Interfaces The interfaces included in the processor for external access include external AHB Lite interface Debug Access Port DAP ...

Page 21: ... a fast single cycle array as a 32 cycle iterative multiplier The iterative multiplier has no impact on interrupt response time because the processor abandons multiply operations to take any pending interrupt Table 1 1 Processor configurable options Feature Configurable option Interrupts External interrupts 1 2 4 8 16 24 or 32 Data endianness Little endian or big endian SysTick timer Present or ab...

Page 22: ... If you are programming the processor then contact the implementer to determine the build configuration of the implementation what integration if any was performed before implementing the processor the integrator to determine the input configuration of the device that you are using Integration and Implementation Manual The Integration and Implementation Manual IIM describes The available build con...

Page 23: ...ntegration choices affect the behavior and features of the processor For MCUs often a single design team integrates the processor before synthesizing the complete design Alternatively the team can synthesise the processor on its own or partially integrated to produce a macrocell that is then integrated possibly by a separate team The operation of the final device depends on Build configuration The...

Page 24: ...ations described in ARM architecture Advanced Microcontroller Bus Architecture Debug Access Port architecture This TRM complements architecture reference manuals architecture specifications protocol specifications and relevant external standards It does not duplicate information from these sources ARM architecture The processor implements the ARMv6 M architecture profile See the ARMv6 M ARM Advanc...

Page 25: ... ARM DDI 0432C Copyright 2009 ARM Limited All rights reserved 1 9 ID112415 Non Confidential 1 6 Product revisions This section describes the differences in functionality between product revisions r0p0 First release ...

Page 26: ...Introduction 1 10 Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 27: ...ited All rights reserved 2 1 ID112415 Non Confidential Chapter 2 Functional Description This chapter provides an overview of the processor functions It contains the following sections About the functions on page 2 2 Interfaces on page 2 4 ...

Page 28: ...ly an ARMv6 M compliant 24 bit SysTick timer A 32 bit hardware multiplier This can be the standard single cycle multiplier or a 32 cycle multiplier that has a lower area and performance implementation The system interface supports either little endian or byte invariant big endian data accesses The ability to have deterministic fixed latency interrupt handling Load store multiples and multicycle mu...

Page 29: ...ort Optional debug support Zero to four hardware breakpoints Zero to two watchpoints Program Counter Sampling Register PCSR for non intrusive code profiling if at least one hardware data watchpoint is implemented Single step and vector catch capabilities Support for unlimited software breakpoints using BKPT instruction Non intrusive access to core peripherals and zero waitstate system slaves throu...

Page 30: ...sses and debug accesses share the external interface to external AHB peripherals The processor accesses take priority over debug accesses Any vendor specific components can populate this bus 2 2 2 Debug Access Port The processor has a low gate count Debug Access Port DAP This provides a Serial Wire or JTAG debug port and connects to the processor slave port to provide full system level debug acces...

Page 31: ...s chapter provides an overview of the application level programmers model It contains the following sections About the programmers model on page 3 2 Modes of operation and execution on page 3 3 Instruction set summary on page 3 4 Memory model on page 3 9 Processor core registers summary on page 3 11 Exceptions on page 3 12 ...

Page 32: ...hapter gives an overview of the Cortex M0 programmers model that describes the implementation defined options It also contains the ARMv6 M Thumb instructions it uses and their cycle counts for the processor In addition Chapter 4 summarizes the system control features of the programmers model Chapter 5 summarizes the NVIC features of the programmers model Chapter 6 summarizes the Debug features of ...

Page 33: ...ARMv6 M Architecture Reference Manual for information about the modes of operation and execution Note Other ARM architectures support the concept of privileged or unprivileged software execution This processor does not support different privilege levels Software execution is always privileged meaning software can access all the features of the processor ...

Page 34: ... counts The cycle counts are based on a system with zero wait states Table 3 1 Cortex M0 instruction summary Operation Description Assembler Cycles Move 8 bit immediate MOVS Rd imm 1 Lo to Lo MOVS Rd Rm 1 Any to Any MOV Rd Rm 1 Any to PC MOV PC Rm 3 Add 3 bit immediate ADDS Rd Rn imm 1 All registers Lo ADDS Rd Rn Rm 1 Any to Any ADD Rd Rd Rm 1 Any to PC ADD PC PC Rm 3 8 bit immediate ADDS Rd Rd im...

Page 35: ...cal shift left by register LSLS Rd Rd Rs 1 Logical shift right by immediate LSRS Rd Rm shift 1 Logical shift right by register LSRS Rd Rd Rs 1 Arithmetic shift right ASRS Rd Rm shift 1 Arithmetic shift right by register ASRS Rd Rd Rs 1 Rotate Rotate right by register RORS Rd Rd Rs 1 Load Word immediate offset LDR Rd Rn imm 2 Halfword immediate offset LDRH Rd Rn imm 2 Byte immediate offset LDRB Rd ...

Page 36: ...gister offset STR Rd Rn Rm 2 Halfword register offset STRH Rd Rn Rm 2 Byte register offset STRB Rd Rn Rm 2 SP relative STR Rd SP imm 2 Multiple STM Rn loreglist 1 Nb Push Push PUSH loreglist 1 Nb Push with link register PUSH loreglist LR 1 Nb Pop Pop POP loreglist 1 Nb Pop and return POP loreglist PC 4 Nc Branch Conditional B cc label 1 or 3d Unconditional B label 3 With link BL label 4 With excha...

Page 37: ...gister MSR specreg Rn 4 Breakpoint BKPT imm e Hint Send event SEV 1 Wait for event WFE 2f Wait for interrupt WFI 2f Yield YIELDg 1 No operation NOP 1 Barriers Instruction synchronization ISB 4 Data memory DMB 4 Data synchronization DSB 4 a Depends on multiplier implementation b N is the number of elements c N is the number of elements in the stack pop list including PC and assumes load or store do...

Page 38: ...x M profile processors To ensure a smooth transition ARM recommends that code designed to operate on other Cortex M profile processor architectures obey the following rules and configure the Configuration Control Register CCR appropriately use word transfers only to access registers in the NVIC and System Control Space SCS treat all unused SCS registers and register fields on the processor as Do N...

Page 39: ...cesses below 0xE0000000 or above 0xF0000000 appear as AHB Lite transactions on the AHB Lite master port of the processor Accesses in the range 0xE0000000 to 0xEFFFFFFF are handled within the processor and do not appear on the AHB Lite master port of the processor The processor supports only word size accesses in the range 0xE0000000 0xEFFFFFFF Table 3 2 shows the code data and device suitability f...

Page 40: ...served ARM DDI 0432C Non Confidential ID112415 Note Regions not marked as suitable for code behave as Execute Never XN and generate a HardFault exception if code attempts to execute from this location See the ARMv6 M ARM for more information about the memory model ...

Page 41: ... the stack pointer to use Main Stack Pointer MSP or Process Stack Pointer PSP PSP R13 LR R14 The Link Register LR is register R14 It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC is register R15 It contains the current program address PSR The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program S...

Page 42: ...ead sensitive or sensitive to repeated writes The software must not use these instructions in any case where repeated reads or writes might cause inconsistent results or unwanted side effects The processor implementation can ensure that a fixed number of cycles are required for the NVIC to detect an interrupt signal and the processor fetch the first instruction of the associated interrupt handler ...

Page 43: ...ts reserved 4 1 ID112415 Non Confidential Chapter 4 System Control This chapter summarizes the system control registers and their structure It contains the following sections About system control on page 4 2 System control register summary on page 4 3 ...

Page 44: ...opyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 4 1 About system control This section describes the system control registers that control and configure various system control functions ...

Page 45: ... SYST_CSR SysTick Control and Status Register in the ARMv6 M ARM SYST_RVR Unknown SysTick Reload Value Register in the ARMv6 M ARM SYST_CVR Unknown SysTick Current Value Register in the ARMv6 M ARM SYST_CALIB Implementation defineda SysTick Calibration value Register in the ARMv6 M ARM CPUID 0x410CC200 See CPUID Register on page 4 4 ICSR Interrupt Control State Register in the ARMv6 M ARM AIRCR 0x...

Page 46: ...register bit assignments 31 16 15 4 3 0 Implementer Revision Partno 24 23 20 19 Variant Constant Table 4 2 CPUID bit register assignments Bits Field Function 31 24 Implementer Implementer code 0x41 ARM 23 20 Variant Implementation defined In ARM implementations this is the major revision number n in the rn part of the rnpn revision status Product revision status on page xii 0x0 19 16 Constant Indi...

Page 47: ... reserved 5 1 ID112415 Non Confidential Chapter 5 Nested Vectored Interrupt Controller This chapter summarizes the Nested Vectored Interrupt Controller NVIC It contains the following sections About the NVIC on page 5 2 NVIC register summary on page 5 3 ...

Page 48: ... Processor exception handling is described in Exceptions on page 3 12 5 1 1 SysTick timer option The implementation can include a 24 bit SysTick system timer that extends the functionality of both the processor and the NVIC When present the NVIC part of the extension provides a 24 bit system timer SysTick additional configurable priority SysTick interrupt See the ARMv6 M ARM for more information 5...

Page 49: ...ee the ARMv6 M ARM for more information about the NVIC registers and their addresses access types and reset values Table 5 1 NVIC registers Name Description ISER Interrupt Set Enable Register in the ARMv6 M ARM ICER Interrupt Clear Enable Register in the ARMv6 M ARM ISPR Interrupt Set Pending Register in the ARMv6 M ARM ICPR Interrupt Clear Pending Register in the ARMv6 M ARM IPR0 IPR7 Interrupt P...

Page 50: ...Nested Vectored Interrupt Controller 5 4 Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...

Page 51: ...ght 2009 ARM Limited All rights reserved 6 1 ID112415 Non Confidential Chapter 6 Debug This chapter summarizes the debug system It contains the following sections About debug on page 6 2 Debug register summary on page 6 9 ...

Page 52: ...Mv6 M ARM for more information The debug option might include either or both a breakpoint unit supporting 1 2 3 or 4 hardware breakpoints a watchpoint unit supporting 1 or 2 watchpoints The processor implementation can be partitioned to place the debug components in a separate power domain from the processor core and NVIC When debug is implemented ARM recommend that a debugger identifies and conne...

Page 53: ...a debugger identifies the SCS from its CoreSight identification it can identify the processor and its revision number from the CPUID register offset at 0xD00 in the SCS 0xE000ED00 A debugger cannot rely on the Cortex M0 ROM table being the first ROM table encountered One or more system ROM tables are required between the access port and the Cortex M0 ROM table if other CoreSight components are in ...

Page 54: ... Cortex M0 ROM table identification values Register Value Description Peripheral ID4 0x00000004 Component and peripheral ID register formats in the ARMv6 M ARM Peripheral ID0 0x00000071 Peripheral ID1 0x000000B4 Peripheral ID2 0x0000000B Peripheral ID3 0x00000000 Component ID0 0x0000000D Component ID1 0x00000010 Component ID2 0x00000005 Component ID3 0x000000B1 Table 6 2 Cortex M0 ROM table compon...

Page 55: ...cation Table 6 3 shows the SCS CoreSight identification registers and values for debugger detection Final debugger identification of the Cortex M0 processor is through the CPUID register in the SCS see CPUID Register on page 4 4 See the ARMv6 M ARM and the ARM CoreSight Components Technical Reference Manual for more information about the SCS CoreSight identification registers and their addresses a...

Page 56: ...dress masking as described in the ARMv6 M ARM DWT CoreSight identification Table 6 4 shows the DWT identification registers and values for debugger detection See the ARMv6 M ARM and the ARM CoreSight Components Technical Reference Manual for more information about the DWT CoreSight identification registers and their addresses and access types Table 6 4 DWT identification values Register Value Desc...

Page 57: ...tation provides between zero and four breakpoint registers A processor configured with zero breakpoints implements no breakpoint functionality and the ROM table shows that no BPU is implemented BPU functionality The processor breakpoints implement PC based breakpoint functionality as described in the ARMv6 M ARM BPU CoreSight identification Table 6 5 shows the BPU identification registers and thei...

Page 58: ...rights reserved ARM DDI 0432C Non Confidential ID112415 See the ARMv6 M ARM and the ARM CoreSight Components Technical Reference Manual for more information about the BPU CoreSight identification registers and their addresses and access types ...

Page 59: ...r in the ARMv6 M ARM DCRSR Debug Core Register Selector Register in the ARMv6 M ARM DCRDR Debug Core Register Data Register in the ARMv6 M ARM DEMCR Debug Exception and Monitor Control Register in the ARMv6 M ARM Table 6 7 BPU register summary Name Description BP_CTRL Breakpoint Control Register in the ARMv6 M ARM BP_COMP0 Breakpoint Comparator Registers in the ARMv6 M ARM BP_COMP1 BP_COMP2 BP_COM...

Page 60: ...e ARMv6 M ARM for more information about the debug registers and their addresses access types and reset values DWT_COMP1 Comparator Register in the ARMv6 M ARM DWT_MASK1 Mask Register in the ARMv6 M ARM DWT_FUNCTION1 Function Register in the ARMv6 M ARM Table 6 8 DWT register summary continued Name Description ...

Page 61: ...on Affects First Release Table A 2 Differences between issue A and issue B Change Location Affects Update to the product documentation information Product documentation design flow and architecture on page 1 6 All revisions Update to the instruction set summary Instruction set summary on page 3 4 All revisions Clarification of the processor core register set summary Processor core registers summar...

Page 62: ...Revisions A 2 Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 Table A 3 Differences between issue B and issue C Change Location Affects No technical changes ...

Page 63: ...mends only a subset of the protocol is usually used This subset is defined as the AMBA AHB Lite protocol See also Advanced Microcontroller Bus Architecture and AHB Lite Advanced Microcontroller Bus Architecture AMBA A family of protocol specifications that describe a strategy for the interconnect AMBA is the ARM open standard for on chip buses It is an on chip bus specification that details a stra...

Page 64: ...ecture The organization of hardware and or software that characterizes a processor and its attached components and enables devices with similar characteristics to be grouped together when describing their behavior for example Harvard architecture instruction set architecture ARMv6 M architecture Big endian Byte ordering scheme in which bytes of decreasing significance in a data word are stored at ...

Page 65: ...s together with custom hardware that supports software debugging Endianness Byte ordering The scheme that determines the order that successive bytes of a data word are stored in memory An aspect of the system s memory mapping See also Little endian and Big endian Exception An error or event which can cause the processor to suspend the currently executing instruction stream and execute a specific e...

Page 66: ... processing operations only operate on register contents not directly on memory contents Multi layer An interconnect scheme similar to a cross bar switch Each master on the interconnect has a direct link to each slave The link is not shared with other masters This enables each master to process transfers in parallel with other masters Contention only occurs in a multi layer interconnect at a paylo...

Page 67: ...fword aligned Thumb state A processor that is executing Thumb 16 bit halfword aligned instructions is operating in Thumb state Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned For example a word stored at an address that is not divisible by four Unpredictable For reads the data returned when reading from this...

Page 68: ...Glossary Glossary 6 Copyright 2009 ARM Limited All rights reserved ARM DDI 0432C Non Confidential ID112415 ...