System Control
ARM DDI 0432C
Copyright © 2009 ARM Limited. All rights reserved.
4-3
ID112415
Non-Confidential
4.2
System control register summary
Table 4-1 gives the system control registers. Each of these registers is 32 bits wide.
Note
•
All system control registers are only accessible using word transfers. Any attempt
to read or write a halfword or byte is Unpredictable.
•
If the processor is implemented without the SysTick timer, the SYST_CSR,
SYST_RVR, SYST_CVR, and SYST_CALIB register reads as zero, writes
ignored RAZ/WI.
•
See the
ARMv6-M ARM
for more information about the system control registers,
and their addresses and access types, and reset values not shown in Table 4-1.
Table 4-1 System control registers
Name
Reset
value
Description
SYST_CSR
-
SysTick Control and Status Register
in the
ARMv6-M ARM
SYST_RVR
Unknown
SysTick Reload Value Register
in the
ARMv6-M ARM
SYST_CVR
Unknown
SysTick Current Value Register
in the
ARMv6-M ARM
SYST_CALIB
Implementation-defined
a
SysTick Calibration value Register
in the
ARMv6-M ARM
CPUID
0x410CC200
See
ICSR
-
Interrupt Control State Register
in the
ARMv6-M ARM
AIRCR
0x00000000
b
0x00008000
c
Application Interrupt and Reset Control Register
in the
ARMv6-M ARM
CCR -
Configuration and Control Register
in the
ARMv6-M ARM
SHPR2
-
System Handler Priority Register 2
in the
ARMv6-M ARM
SHPR3
-
System Handler Priority Register 3
in the
ARMv6-M ARM
SHCSR -
System Handler Control and State Register
in the
ARMv6-M ARM
a. This value is configured by the implementer during implementation. See the documentation supplied by your implementer
for more information.
b. Little-endian implementation.
c. Big-endian implementation.
