Nested Vectored Interrupt Controller
5-2
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ARM DDI 0432C
Non-Confidential
ID112415
5.1
About the NVIC
External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the Cortex-M0 processor
core are closely coupled, providing low latency interrupt processing and efficient
processing of late arriving interrupts.
All NVIC registers are only accessible using word transfers. Any attempt to read or
write a halfword or byte individually is Unpredictable.
NVIC registers are always little-endian. Processor accesses are correctly handled
regardless of the endian configuration of the processor.
Processor exception handling is described in
5.1.1
SysTick timer option
The implementation can include a 24-bit SysTick system timer, that extends the
functionality of both the processor and the NVIC.
When present, the NVIC part of the extension provides:
•
a 24-bit system timer (SysTick)
•
additional configurable priority SysTick interrupt.
See the
ARMv6-M ARM
for more information.
5.1.2
Low power modes
The implementation can include a WIC. This enables the processor and NVIC to be put
into a very low-power sleep mode leaving the WIC to identify and prioritize interrupts.
The processor fully implements the
Wait For Interrupt
(
WFI
),
Wait For Event
(
WFE
) and
the
Send Event
(
SEV
) instructions. In addition, the processor also supports the use of
SLEEPONEXIT, which causes the processor core to enter sleep mode when it returns
from an exception handler to Thread mode. See the
ARMv6-M ARM
for more
information.
