Arrow Cyclone 10 LP RefKit, User Manual

Page 1: ...Cyclone 10 LP RefKit User Guide Please read the legal disclaimer at the end of this document Revision 1 0 ...

Page 2: ... 3 1 Board Status Elements 11 3 2 Clock Circuitry 11 3 3 Peripherals Connected to the FPGA 12 3 3 1 Communication and Configuration 12 3 3 2 Fast Ethernet 14 3 3 3 Serial Configuration Flash Memory 15 3 3 4 HyperRAM 16 3 3 5 SDRAM Memory 17 3 3 6 QSPI Flash Memory 18 3 3 7 EEPROMs 18 3 3 8 ADC DAC 19 3 3 9 I2C Grove Connector 20 3 3 10 Arduino Header 21 3 3 11 PMOD Connectors 22 3 3 12 VGA 24 3 3 ...

Page 3: ...iplexer 46 5 2 7 Adding the Components to the Schematic 48 5 2 8 Connecting the Components 50 5 2 9 Add inputs outputs to the schematic 53 5 2 10 Analysis and Synthesis 55 5 2 11 Adding Timing Constraints 56 5 2 12 Pinning Assignments 57 5 2 13 Compiling the Design 60 5 2 14 Reading the Compilation Report 61 Configuring the Cyclone 10 LP RefKit 63 6 1 Configure the FPGA in JTAG mode 63 6 2 Serial ...

Page 4: ...Y connection 14 Figure 9 Configuration Flash Connections 16 Figure 10 HyperRAM Connections 16 Figure 11 SDRAM Connections 17 Figure 12 QSPI Flash Connections 18 Figure 13 EEPROM Connections 19 Figure 14 ADC DAC Connections 19 Figure 15 I2C Grove Connector 20 Figure 16 Arduino Header Connections 21 Figure 17 PMOD Headers Connections 22 Figure 18 VGA Connections 24 Figure 19 LED Connections 25 Figur...

Page 5: ...lution for I O expansion chip to chip interfacing industrial automotive and consumer applications The C10LP RefKit is equipped with an Arrow USB Programmer2 2 ports 10 100Mbps Ethernet SDRAM HyperRAM flash memory VGA 8 channel ADC DAC PMODs and ARDUINO connectors making it a fully featured plug and play solution without any additional costs The C10LP RefKit board contains all the tools needed to u...

Page 6: ...Page 6 February 2022 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems Arrow Electronics In Person Arrow EMEA 49 0 6102 5030 0 Online https arrow com Trenz Electronic GmbH https www trenz electronic de en ...

Page 7: ...om view of the board It depicts the layout of the board and indicates the location of the various connectors and key components er Input ast Et ernet rts D eset u n ser LEDs Ds D I ea er laster micr c nnect r C n gura n as mem ry DC D C Cycl ne L ser u ns ser u n ser LEDs C D E LED ri ge erIn icat rLED Digit egment Display I C r eC nnect r yper D Figure 1 Cyclone 10 LP RefKit Board top view ...

Page 8: ...Elements LE 55 856 M9K Memory Kb 2 340 18 x 18 Multiplier 156 PLLs 4 I O 321 Memory Devices 64 256Mbit external SDRAM memory1 64Mbit external HyperRAM memory 64 128Mbit external QSPI Flash memory1 16Mbit EPCQ serial configuration flash memory 2 2Kbit serial MAC Address EEPROM memory 1 The different board variations are equipped with different memory devices Et ernet s I las em ry C ressEE s nal g ...

Page 9: ...oard status LEDs Power Recommended external supply voltage range 5 0 V nominal Recommended external supply current 3 A Recommended I O signal voltage range 0 to 3 3 V 2 2 Hardware variations Multiple board configurations are available with Cyclone 10 LP RefKit have different equipment This user guide covers REV02 hardware revision with 8C and 8CA featured boards These two boards are the same with ...

Page 10: ... Diagram Figure 3 represents the block diagram of the board All the connections are established through the Cyclone 10 LP FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design Figure 3 Cyclone 10 LP RefKit Block Diagram ...

Page 11: ...thout error 3 2 Clock Circuitry All the external clocks of the system can be seen in Figure 5 There are two default clocks which are 12MHz and 25MHz Both clock signals are connected and driving the FPGA s user logic and other interfaces Arrow USB Programmer2 and Ethernet There are optional slots for other clocks that you can either add another preferred clock source to the FPGA CLK_IN_SMA or gener...

Page 12: ... are two types of configuration methods supported by C10LP RefKit 1 JTAG Configuration configuration using JTAG ports JTAG configuration scheme allows you to directly configure the device core through JTAG pins TDI TDO TMS and TCK pins The Quartus Prime software automatically generates a sof that can be downloaded to the Cyclone 10 LP with a download cable through the Quartus Prime Programmer 2 Co...

Page 13: ...TDI PIN_L5 Input Test Data In 3 3 V TMS PIN_L1 Input Test Mode Select 3 3 V For detailed information about how to configure the Cyclone 10 LP please refer to Chapter 6 3 3 1 2 USB Communication The FTDI chip converts signals from USB 2 0 to a variety of standard serial and parallel interfaces Channel A of FTDI chip is used in MPPSE mode for JTAG Channel B is routed to FPGA and is usable for other ...

Page 14: ...bus 3 3 V BCBUS3 PIN_H21 Bidir D 3 of bidirectional data bus 3 3 V BCBUS4 PIN_H22 Bidir D 4 of bidirectional data bus 3 3 V BCBUS5 PIN_J21 Bidir D 5 of bidirectional data bus 3 3 V BCBUS6 PIN_J21 Bidir D 6 of bidirectional data bus 3 3 V BCBUS7 PIN_J19 Bidir D 7 of bidirectional data bus 3 3 V 3 3 2 Fast Ethernet The board has two independent 10 100Mbps Ethernet ports with RJ 45 connectors For the...

Page 15: ... Chip Reset 3 3 V ETH2_INTRP PIN_N17 Bidir Interrupt 3 3 V ETH2_RXC PIN_R17 Bidir MII Receive Clock 3 3 V ETH2_RXER PIN_P17 Bidir MII Receive Error 3 3 V ETH2_RXD0 PIN_M20 Bidir MII Receive Data D 0 3 3 V ETH2_RXD1 PIN_M19 Bidir MII Receive Data D 1 3 3 V ETH2_RXD2 PIN_M16 Bidir MII Receive Data D 2 3 3 V ETH2_RXD3 PIN_N19 Bidir MII Receive Data D 3 3 3 V ETH2_TXC PIN_N16 Bidir MII Transmit Clock ...

Page 16: ...nal count interface called HyperBus Board Reference FPGA Pin No Pin Func Description I O Std HR_CLK PIN_T16 Output Single Ended Clock 3 3 V HR_RW PIN_U13 Bidir Read Write Data Strobe 3 3 V HR_CS PIN_V13 Output Chip Select 3 3 V HR_RESET PIN_U12 Output Hardware Reset 3 3 V HR_D0 PIN_T15 Bidir Data 0 3 3 V HR_D1 PIN_W17 Bidir Data 1 3 3 V HR_D2 PIN_U14 Bidir Data 2 3 3 V HR_D3 PIN_R15 Bidir Data 3 3...

Page 17: ...ddress 10 3 3 V A11 PIN_AA8 Output SDRAM Address 11 3 3 V A12 PIN_AB8 Output SDRAM Address 12 3 3 V A13 PIN_AB9 Output SDRAM Address 13 3 3 V BA0 PIN_Y6 Output SDRAM Bank Address 0 3 3 V BA1 PIN_V7 Output SDRAM Bank Address 1 3 3 V RAS PIN_V8 Output SDRAM Row Address Strobe 3 3 V CAS PIN_Y7 Output SDRAM Column Address Strobe 3 3 V WE PIN_W8 Output SDRAM Write Enable 3 3 V CS PIN_W7 Output SDRAM Ch...

Page 18: ...bit density3 which can operate on up to 166MHz on the board It can be used to store larger size user data or software for Nios II embedded processors Board Reference FPGA Pin No Pin Func Description I O Std F_CS PIN_F15 Output Chip Enable 3 3 V F_CLK PIN_F16 Output Serial Data Clock 3 3 V F_IO0 PIN_G16 Bidir Serial Data 0 3 3 V F_IO1 PIN_D15 Bidir Serial Data 1 3 3 V F_IO2 PIN_E16 Bidir Serial Dat...

Page 19: ...tion points on the board for 2 analog channels while the remaining 6 channels are directly connected to the J4 header of the Arduino interface Board Reference FPGA Pin No Pin Func Description I O Std ADDA_RSTN PIN_V4 Output Reset 3 3 V ADDA_SYNC PIN_R5 Output Synchronization 3 3 V MCLK PIN_T5 Output Serial Clock Input 3 3 V MOSI PIN_T4 Output Master Output Slave Input 3 3 V MISO PIN_R6 Input Maste...

Page 20: ...ard Reference FPGA Pin No Grove Pin Pin Func Description I O Std I2C_SCL PIN_D20 1 Output Serial Clock Line 3 3 V I2C_SDA PIN_F17 2 Bidir Serial Data Line 3 3 V 3 3V 3 PWR 3 3V power to the connector GND 4 PWR Ground output to the connector I C CL I C D r e C nnect r D D Note The FPGA is also directly connected to the J4 connector If AIN5 0 are used as analog input output make sure that the belong...

Page 21: ...al I O 2 3 3 V D3 PIN_J4 J2 4 Bidir Digital I O 3 3 3 V D4 PIN_E4 J2 5 Bidir Digital I O 4 3 3 V D5 PIN_E3 J2 6 Bidir Digital I O 5 3 3 V D6 PIN_D2 J2 7 Bidir Digital I O 6 3 3 V D7 PIN_F2 J2 8 Bidir Digital I O 7 3 3 V D8 PIN_B2 J1 1 Bidir Digital I O 8 3 3 V D9 PIN_B1 J1 2 Bidir Digital I O 9 3 3 V D10 PIN_G3 J1 3 Bidir Digital I O 10 3 3 V D11 PIN_H2 J1 4 Bidir Digital I O 11 3 3V D12 PIN_F1 J1...

Page 22: ...nnector n c J3 8 Not connected AIN0 PIN_J6 J4 1 Bidir GPIO 0 3 3 V AIN1 PIN_H1 J4 2 Bidir GPIO 1 3 3 V AIN2 PIN_J2 J4 3 Bidir GPIO 2 3 3 V AIN3 PIN_J1 J4 4 Bidir GPIO 3 3 3 V AIN4 PIN_J3 J4 5 Bidir GPIO 4 3 3 V AIN5 PIN_J5 J4 6 Bidir GPIO 5 3 3 V 3 3 11 PMOD Connectors The C10LP RefKit board offers connectivity to PMOD compatible connectors making it possible to add a big variety of sensors or ICs...

Page 23: ... PIN_B4 P3 4 Bidir PMOD I O 4 of P3 3 3 V P3_IO5 PIN_B6 P3 7 Bidir PMOD I O 5 of P3 3 3 V P3_IO6 PIN_A6 P3 8 Bidir PMOD I O 6 of P3 3 3 V P3_IO7 PIN_C6 P3 9 Bidir PMOD I O 7 of P3 3 3 V P3_IO8 PIN_A5 P3 10 Bidir PMOD I O 8 of P3 3 3 V P4_IO1 PIN_A7 P4 1 Bidir PMOD I O 1 of P4 3 3 V P4_IO2 PIN_B7 P4 2 Bidir PMOD I O 2 of P4 3 3 V P4_IO3 PIN_A8 P4 3 Bidir PMOD I O 3 of P4 3 3 V P4_IO4 PIN_B8 P4 4 Bi...

Page 24: ...tivity that allows users to display content on a monitor The VGA uses a 4 bit resistor network DAC which supports up to 640 480 resolutions at a 60Hz refresh rate with 4096 colors Board Reference FPGA Pin No Pin Func Description I O Std VGA_R0 PIN_R3 Output VGA Red 0 3 3 V VGA_R1 PIN_V2 Output VGA Red 1 3 3 V VGA_R2 PIN_W2 Output VGA Red 2 3 3 V VGA_R3 PIN_Y2 Output VGA Red 3 3 3 V VGA_G0 PIN_Y1 O...

Page 25: ...e is a total of 13 red user controllable LEDs connected to the FPGA in two types of splits 8 LEDs are arranged in a traditional row and an additional 5 LEDs are arranged in a joystick shape according to the location of the pushbuttons Each LED is driven directly and individually by the Cyclone 10 LP FPGA driving its associated pin to a high logic level for on or low logic level for off Board Refer...

Page 26: ... to interact with the Cyclone 10 LP FPGA device 5 of them are placed in a joystick shape for better usability Push buttons drive their associated pins low logic level when pressed and high logic level when released Board Reference FPGA Pin No Pin Func Description I O Std RESET PIN_K5 Input nCONFIG 3 3 V USER_BTN1 PIN_U10 Input User button 3 3 V USER_BTN2 PIN_U11 Input User button 3 3 V USER_BTN3 P...

Page 27: ... V SEG_AN1 PIN_F20 AN1 Output Common Anode for Digit 1 3 3 V SEG_AN2 PIN_H16 AN2 Output Common Anode for Digit 2 3 3 V SEG_AN3 PIN_J20 AN3 Output Common Anode for Digit 3 3 3 V SEG_AN4 PIN_K17 AN4 Output Common Anode for Digit 4 3 3 V SEG_CA PIN_J17 A Output Segment A or L1 3 3 V SEG_CB PIN_H17 B Output Segment B or L2 3 3 V SEG_CC PIN_G17 C Output Segment C or L3 3 3 V SEG_CD PIN_G18 D Output Seg...

Page 28: ... is powered through a 2 0mm DC Jack connector All devices are powered by a 3 3V voltage line and the 5V and 3 3V lines are fed back to the Arduino header to power that connection if needed The Cyclone 10 LP FPGA is powered by 2 Enpirion devices DI I DI I DI I DI I C D D E L L L C D E D C D E D C D E D C D E D L L L DI I DI I DI I DI I C D E D Figure 22 Quadruple Seven segment LED Display s Interna...

Page 29: ...e 10 LP RefKit User Guide www arrow com Page 29 February 2022 DC ac scillat rs Ds rr laster Et ernet s E C yper D I las EE s DC D C I C r e r uin Circuit r tec n L C I E I E I Figure 23 Power Tree Connections ...

Page 30: ...ng systems 4 1 Installing Quartus Prime Software 4 1 1 Go to the Intel Download Center Link 4 1 2 Select Windows as the operating system highlighted in red 4 1 3 Select Release 21 1 or your preferred version highlighted in red 4 1 4 Download t e f ll ing files fr m t e In i i ual iles ta highlighted in yellow Quartus Prime Lite Edition Free Questa Intel FPGA Edition includes Starter Edition Cyclon...

Page 31: ...ammer2 to be able to connect to the C10LP RefKit board 4 2 Installing Arrow USB Programmer2 The Cyclone 10 LP RefKit board uses version 2 of the Arrow USB Programmer2 programming solution that is an FTDI FT2232H Hi Speed USB controller plus a programmer DLL Since this FTDI USB controller is a very common standard device usually no specific drivers are needed to make the C10LP RefKit work 4 2 1 Dow...

Page 32: ...he registry of the PC 4 2 3 After connecting the C10LP RefKit board to the PC two unknown devices might appear in t e t er e ices secti n f e ice manager f t e C Windows usually automatically finds the appropriate drivers for these devices After some time t e t er e ices secti n s ul e empty Instea t erial C n erters should be listed in the secti n erial us c ntr llers urt erm re a erial rt s ul e...

Page 33: ...ition can be used free of charge you need to generate a free license for it 4 3 1 Log in to Intel FPGA Self Service Licensing Center 4 3 2 Go to Sign up for Evaluation or Free Licenses tab 4 3 3 Select Questa Intel FPGA Starter Edition SW QUESTA option 4 3 4 Set the seats and accept the terms of use this license 4 3 5 Click on Get License button 4 3 6 In the pop up window select New computer under...

Page 34: ...10 LP RefKit 5 1 1 Launch Quartus Prime Lite Edition from the Start Menu 5 1 2 In the Quartus Prime tool create a new project File New Project Wizard The New Project Wizard walks you through the project settings such as the name directories files directories device family and other settings These settings can be changed later if needed 5 1 3 Click Next ...

Page 35: ...ebruary 2022 5 1 4 Browse in the project directory and choose a preferred location for the new project Then create new folder named C10LPRefKit_blinky This will be the folder containing all the project files 5 1 5 Enter the project name t p 5 1 6 Click Next ...

Page 36: ...pe In this tutorial a new project will be created and thus the default settings of empty project should be selected 5 1 8 Click Next 5 1 9 Add Project Files The Add File window will appear For this tutorial new design files will be created so no files will be added For other designs files could be added here 5 1 10 Click Next ...

Page 37: ... used to select the correct family package pin count and speed grade Quartus Prime will use these settings to compile the design and also provide the programming file that you will use later to program the device 5 1 12 Click Next 5 1 13 EDA Tool Settings In the EDA tool Settings window disable any EDA tools if there are any present EDA tools are third party tools that work with Quartus Prime for ...

Page 38: ...w arrow com Page 38 February 2022 5 1 14 Click Next 5 1 15 Project Summary Page This is the Summary Page that shows the settings Quartus Prime will use for this Project Those settings can be changed if required later 5 1 16 Click Finish ...

Page 39: ... that will be built with the following steps will look as follows when complete 5 2 2 Components of the Design There are three components in the system a PLL a counter and a mux The components in the following steps will be built separately and then connected together A user push button on the board controls the mux The mux in turn control which of the counter outputs slow counting or fast countin...

Page 40: ...window is open by default when you open Quartus Prime If it s not present you can open it by going to the tab Tool IP Catalog 5 2 4 Create and Configure PLL In the IP Catalog browse for ALTPLL via Basic Functions Clocks PLLs and Resets PLL or type in t e searc fiel f r LL 5 2 4 1 In the Search bar of the IP Catalog type pll and select ALTPLL which stands for Altera Phase Locked Loop ...

Page 41: ...eated 5 2 4 3 Click OK The next step is to configure the PLL component that we just named 5 2 4 4 Enter the PLL reference clock frequency to match the clock input on the C10LP RefKit Board We have 12 MHz and 25MHz clock signals coming into the FPGA in this example we will use 12MHz for the inclk0 input The setting should look like this 5 2 4 5 Click Next 5 2 4 6 Simplify the PLL by disabling arese...

Page 42: ...om Pages 3 to Pages 5 but leaving the default options as they are The page numbers can be seen on the top of the window 5 2 4 9 On page 6 c0 Core External Output Clock select Enter utput cl c frequency an set the requested setting to 20 MHz leave the rest as default For simplification there is one input to the PLL 12 MHz and one output of the PLL 20 MHz ...

Page 43: ...matic design we will be creating later 5 2 4 12 Click Finish The PLL 1st component will now be created 5 2 4 13 If this is the first time that you are using this version of Quartus Prime you might see a pop up Window for Quartus Prime IP Files that asks if the tool should add IP files automatically after generating them 5 2 4 14 elect ut matically a uartus Prime IP Files to all projects 5 2 4 15 C...

Page 44: ...t e L C E r type c unter in t e searc fiel Note that the LPM stands for Library of Parameterized Modules 5 2 5 2 Click Add 5 2 5 3 en t e a e I ariati n p p up appears enter simple c unter an select DL as below 5 2 5 4 Click OK 5 2 5 5 The next step is to increase the size of the counter to a number of bits large enough to divide down the clock so we can see the LEDs toggling 5 2 5 6 Change this n...

Page 45: ...er Guide www arrow com Page 45 February 2022 5 2 5 8 Select Next until reaching Page 5 5 2 5 9 Select simple_counter bsf checkbox to generate a symbol for our schematic design 5 2 5 10 Click Finish The counter is now created ...

Page 46: ...l be seen on the LEDs 5 2 6 1 To create this mux select IP Catalog and expand Basic Functions Miscellaneous and select LPM_MUX or type mux in the search field 5 2 6 2 Click Add 5 2 6 3 In the Save IP Variation enter the name of the counter_mux and the file type to be VHDL 5 2 6 4 Click OK 5 2 6 5 Select 2 data inputs and the width of the input and output buses to be 8 bits The reason for 8 bits is...

Page 47: ...clone 10 LP RefKit User Guide www arrow com Page 47 February 2022 5 2 6 6 Click Next until Page 3 5 2 6 7 Select counter_mux bsf checkbox to generate a symbol for our schematic design 5 2 6 8 Click Finish ...

Page 48: ...nts together 5 2 7 1 To do so select File menu then select New and select Block Diagram Schematic File 5 2 7 2 Click OK A new schematic will be created where the components can be added 5 2 7 3 Right click on the schematic page and select Insert Symbol as seen below 5 2 7 4 In the new window expand Project and the three components that were created can now be seen ...

Page 49: ...in the steps from 5 2 7 3 to 5 2 7 6 do the same for counter_mux and simple_counter to add them to the schematic page The order of adding the components does not matter as the connections between them will happen in the following steps 5 2 7 9 After adding three components your schematic should look similar to the following To place them similarly simply drag the components to the appropriate loca...

Page 50: ...omponents Next step is to make the proper connections between the three components we just added to the schematic 5 2 8 1 Select the ode Tool 5 2 8 2 Connect the c0 of the PLL to the simple_counter as shown below This will mean that a single signal c0 is connected to the simple_counter clock ...

Page 51: ...create a connection coming out of the simple_counter and one connection for each of the inputs of the counter_mux as show below 5 2 8 5 Right click on the output bus of the simple counter that you just created and select Properties Set the name of the bus to counter 31 0 The view of the Bus Properties should look like this ...

Page 52: ...ide www arrow com Page 52 February 2022 5 2 8 6 Clic 5 2 8 7 Do the same for input buses of the mux Name the top bus input data1x 7 0 counter 24 31 Name the bottom bus input data0x 7 0 counter 19 26 Schematic should look like this ...

Page 53: ...inclk0 of the PLL and add other one input pin for sel of counter_mux Your schematic should look like this 5 2 9 3 Rename the pin_name1 to CLK12M by double clicking its current name This is going to be the clock signal coming into the FPGA 5 2 9 4 Rename the pin_name2 to USER_BTN by double clicking its current name This is going to be one of the user buttons of the C10LP RefKit board to select the ...

Page 54: ...nter_mux component Your schematic should look like this now 5 2 9 6 Click on the Pin Tool as before but this time select Output 5 2 9 7 Add one output pin for the LEDs 5 2 9 8 Rename the pin to LED 7 0 5 2 9 9 Using the Bus Tool make the connection between counter_mux component and output pin result 7 0 LED 7 0 The final schematic should look like the following ...

Page 55: ...unter The signals of the counter that are not connected will not be used by Quartus Prime 5 2 9 10 Save your design Open the File Menu and select Save Save it as top bdf 5 2 10 Analysis and Synthesis The next step is to run Analysis and Synthesis to ensure that there are no errors in the design To run Analysis and synthesis open Processing Start Analysis and Synthesis or from clicking button on th...

Page 56: ..._path from get_ports USER_BTN set_false_path from to get_ports LED The first line create cl c tells Quartus Prime that the clock CLK12M is 83 333 ns 12 MHz It also assigns the CLK12M to a pin port in the sdc format The second line eri e pll cl c s tells the software to look if there are any PLLs and if so automatically derive the clock multiplication division of the outputs of the PLL even if they...

Page 57: ... be downloaded to the FPGA pin assignments that match the hardware on the board are needed There are different ways to do this such as the Pin Planner Assignment Editor and text files The following steps will show one of these ways the Pin Planner Since there are only 10 pins that need to be assigned the Pin Planner can be used If many pins are needed other ways can be used such as the Quartus Ass...

Page 58: ...ew of the FPGA or alternatively set the Location field of the CLK12M to PIN_G21 Note that the Location of the CLK12M is now set to Location PIN_G21 as seen in blue colour in the top view of the FPGA 5 2 12 3 The other pins need to be assigned as well Just like previously set all the pins to their appropriate locations using the table below by either drag and drop or writing manually the location ...

Page 59: ...in Planner should look like this after assigning all the pin locations 5 2 12 5 The specific pins are now selected but the I O standards now need to be set as well The button LEDS and clock pins are the same I O standard for C10LP RefKit since all banks and peripherals are powered by 3 3V The USER_BTN the LEDs and clock pins are 3 3 V LVTTL These I O standards can be set in the Pin Planner by sele...

Page 60: ... settings are automatically saved 5 2 13 Compiling the Design 5 2 13 1 You can set the default I O Standard which can eliminate some design warning and save you time from setting the standard for some pins manually Open Assignments Device Device and Pin Options Voltage and set Default I O Standard to 3 3 V LVTTL and press OK to all the windows ...

Page 61: ...rt Compilation or push the button on the toolbar If there are errors they will need to be resolved and re compiled before the design can be programmed to the board When Compiling finishes and there are no errors there will be a message at the bottom of the window that states Full Compilation was successful and a 100 indication along with the compile time in the right bottom corner 5 2 14 Reading t...

Page 62: ...e seen in Resource Usage Summary as well how many LEs were used for each component in Resource Utilization by Entity In the Fitter more detailed information about the pins and their banks can be seen Timing Analyzer shows various timing information concerning the design as well as if the design has met the timing requirements In this case timing requirements were met but in other cases that requir...

Page 63: ...e 6 1 1 Connect your C10LP RefKit board to a power supply and then to your PC using an USB cable Since t e rr laster s ul e alrea y installe t e in s De ice Manager should display the following entries are highlighted in red port number may differ depending on your PC If the Arrow USB Blaster is not installed please refer to Chapter 4 2 for installing the drivers 6 1 2 Open the Quartus Prime Progr...

Page 64: ...w 6 1 4 Click Hardware Setup and double click Arrow USB Blaster entry in the Hardware Setup tab The Currently selected hardware should now show Arrow USB Blaster USB0 depending on your PC the USB port number may variant 6 1 5 Click Close 6 1 6 Make sure the hardware setup is Arrow USB Blaster USB0 and the mode is JTAG If the Mode is not set to JTAG click on it and select JTAG from the drop down me...

Page 65: ... the following steps and continue with the 6 1 12 point 6 1 8 Clic ut Detect n t e left si e f t e r grammer 6 1 9 Select 10CL055Y e ice an clic n t e elect Device window 6 1 10 Double click none to choose programming file 6 1 11 Navigate to project_directory output_files in your compilation directory Select and open the top sof file ...

Page 66: ...omplete the Progress bar should reach 100 Successful The design is now programmed to the FPGA Note that turning off and then on the FPGA will result into losing its configuration 6 2 Serial configuration flash memory programming The configuration data to be written to EPCQ A will be part of the JTAG indirect configuration file jic This configuration data is automatically loaded from the serial con...

Page 67: ...rime go to File Convert Programming Files 6 2 1 2 Set the programming file type to JTAG Indirect Configuration File jic 6 2 1 3 Click on the button for configuration device 6 2 1 4 Select Cyclone 10 LP for the Device family choose EPCQ16A from the Configuration device tab and make sure that the Active Serial is set to mode ...

Page 68: ...2 6 2 1 5 Click OK Now the output programming file settings should look like this 6 2 1 6 Select Flash Loader under Input files to covert settings and click on dd evice button 6 2 1 7 On the new window select Cyclone 10 LP as Device family and 10CL055Y as Device name ...

Page 69: ...lick OK to add device to Flash Loader 6 2 1 9 Select SOF Data under Input files to convert and click on dd File button 6 2 1 10 Go to project_directory output_files and open top sof 6 2 1 11 Make sure that your settings are same as the picture below and if everything is correct ...

Page 70: ...Programming 6 2 2 1 Open Programmer 6 2 2 2 Select output_files top sof and click Change File button 6 2 2 3 Go to project_directory output_files and open output_file jic When you add the jic file the Programmer will automatically update the JTAG chain and put EPCQ A flash memory 6 2 2 4 Make sure the Programmer shows the correct file and correct parts in the JTAG chain and check the Program Confi...

Page 71: ...can simply reconfigure the FPGA with our program by pushing RESET button which will reset the FPGA and automatically loads the configuration from EPCQ A 6 3 Testing the Design Does not matter which way the C10LP RefKit was configured the results should be the same for both methods with the only difference being if configuration is retained after power off On the board by default the LEDS should no...

Page 72: ...s and Fixes 1 Issue In some rare cases when using Windows 10 operating system the programmer DLL is not properly loaded unloaded causing the Quartus Programmer to not detect the Arrow USB Programmer2 Solution Restart the Altera JTAG Server using the Services application of Windows ...

Page 73: ...Cyclone 10 LP RefKit User Guide www arrow com Page 73 February 2022 Appendix 8 1 Revision History Version Change Log Date of Change V1 0 Initial Version 17 02 2022 ...

Page 74: ...tion system and it may not be offered for sale or lease or sold leased or otherwise distributed for commercial purposes OWNERSHIP AND COPYRIGHT Title to the Evaluation Board remains with Arrow and or its licensors This Agreement does not involve any transfer f intellectual pr perty rig ts I f r e aluati n ar u may n t rem e any c pyrig t r t er proprietary rights notices without prior written auth...

Page 75: ...d under this Agreement You shall indemnify Arrow and its Affiliates and Licensors against and pay any resulting costs and damages finally awarded against Arrow and its Affiliates and Licensors or agreed to in any settlement provided that You have sole control of the defense and settlement of the claim or action and Arrow cooperates in the defense and furnishes all related evidence under its contro...