SharpMedia PCIE-8120 Hardware Description
SharpMedia™ PCIE-8120 Installation and Use (6806800R89F
)
88
The OCT2224M is composed of five major subsystems:
The Opus2 DSP subsystem
The DDR Memory Subsystem
The High-speed I/O Subsystem (Ethernet MAC Engines)
The Resources Subsystem (GPIO)
The Maintenance Subsystem (Boot Controller)
The main features of the OCT2224M are:
24 Opus2 cores with 144k bytes of L1 memory per core
C programmable DSP
484-Pin BGA 1.0mm pitch
4W typical power consumption
Secure custom booting capability
Precision clock synchronization on external references
Various Peripheral Interfaces Ethernet, serial/parallel hi-speed interfaces, TDM, Flash, and
so on. For details, see document
OCT2200MDS8000
listed in
Table "Related Specifications"
.
B.9.2
DDR3 Memory Subsystem
The 32-bit DDR memory controller is used for interface to JEDEC DDR3 SDRAM devices. The
interface supports 4.32 GB/s at a 1080 MHz data rate (540 MHz clock rate).
The DSP memory on the PCIE-8120 is realized with two DDR3 x16 devices per DSP. The
memory access is 32-bits wide.
The default memory size is 512 MByte.
The DDR3 memory is not used until the DDR configuration is obtained from the boot image.
Summary of Contents for 6806800R89E
Page 1: ...SharpMedia PCIE 8120 Installation and Use P N 6806800R89F November 2016...
Page 8: ...SharpMedia PCIE 8120 Installation and Use 6806800R89F 8 List of Tables...
Page 10: ...SharpMedia PCIE 8120 Installation and Use 6806800R89F 10 List of Figures...
Page 16: ...SharpMedia PCIE 8120 Installation and Use 6806800R89F About this Manual 16 About this Manual...
Page 20: ...SharpMedia PCIE 8120 Installation and Use 6806800R89F Safety Notes 20...
Page 32: ...Functional Description SharpMedia PCIE 8120 Installation and Use 6806800R89F 32...
Page 38: ...Hardware Preparation and Installation SharpMedia PCIE 8120 Installation and Use 6806800R89F 38...
Page 94: ...Known Issues SharpMedia PCIE 8120 Installation and Use 6806800R89F 94...
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