Maps and Registers
ATCA-7360 Installation and Use (6806800J07S)
175
2
Parity Error (PE) indicator
When PE is set, it indicates that the parity of the received data character
does not match the parity selected in the LCR (bit 4). PE is cleared every
time the CPU reads the contents of the LSR. In the FIFO mode, this error is
associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of
the FIFO:
1: Parity error occurred
0: No parity error
0
LPC: r
3
Framing Error (FE) indicator
When FE is set, it indicates that the received character did not have a valid
(set) stop bit. FE is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated
character is at the top of the FIFO. The ACE tries to resynchronize after a
framing error. To accomplish this, it is assumed that the framing error is due
to the next start bit. The ACE samples this start bit twice and then accepts
the input data:
1: Framing error occurred
0: No framing error
0
LPC: r
4
Break Interrupt (BI) indicator
When BI is set, it indicates that the received data input was held low for
longer than a full-word transmission time. A full-word transmission time is
defined as the total time to transmit the start, data, parity, and stop bits. BI
is cleared every time the CPU reads the contents of the LSR. In the FIFO
mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated
character is at the top of the FIFO. When a break occurs, only one 0
character is loaded into the FIFO. The next character transfer is enabled
after RXD goes to the marking state for at least two Receiver CLK samples
and then receives the next valid start bit:
1: Full WORD transmission time exceeded
0: Normal operation
0
LPC: r
Table 6-35 Line Control Register (LCR) (continued)
LPC IO Address: Base + 5
Bit
Description
Default
Access
Summary of Contents for ATCA-7360
Page 1: ...ATCA 7360 Installation and Use P N 6806800J07S May 2016...
Page 26: ...ATCA 7360 Installation and Use 6806800J07S About this Manual 26 About this Manual...
Page 36: ...ATCA 7360 Installation and Use 6806800J07S Sicherheitshinweise 36...
Page 43: ...Introduction ATCA 7360 Installation and Use 6806800J07S 43...
Page 44: ...Introduction ATCA 7360 Installation and Use 6806800J07S 44...
Page 66: ...Installation ATCA 7360 Installation and Use 6806800J07S 66...
Page 258: ...Supported IPMI Commands ATCA 7360 Installation and Use 6806800J07S 258...
Page 284: ...Replacing the Battery ATCA 7360 Installation and Use 6806800J07S 284...
Page 287: ......
