500-003111-000
3-7
conversion digitizes the output of the T&H amplifier into a 12-bit data word, and
then terminates the conversion sequence. The CONV COMPL L flag from the
ADC is HIGH during the conversion, and is LOW otherwise.
Completion of the A/D conversion causes the NEW DATA RDY flag to
be set HIGH, indicating that valid data is present in the Converter Data Register
(Section 4). The action of reading the Converter Data Register resets the NEW
DATA RDY and CONV BUSY flags to the LOW ("0") state. ADC output coding
can be program-selected as either binary or two's complement.
3.4.2
Throughput (Sample Rate) Factors
Total system throughput (sample rate) F
T
can be expressed generally
as:
F
T
= 1/ [n X (T1 + T2 + T3) ],
Where:
F
T
= Throughput (samples per second, per channel)
N = Number of channels
T1 = 3111 settling delay . . . . . . . . . .8-120 µs (Gain x1 to x500)
T2 = 3111 A/D conversion time . . 19 µs
T3 = CPU (controlling processor) time invested per channel
If CPU time is negligible relative to the conversion sequence, then T3
is zero, and the expression for maximum throughput (N=1) is:
F
T
(maximum) = 1 / (T1 + T2)
Maximum throughput for a gain of "x1" then, 37,037 samples per
second for a single input channel.
3.4.3
Interleaved (Pipelined) Operation
By allowing a new channel to settle before conversion of the
previously selected channel has been completed, T
1
will be eliminated from F
T
(maximum). The VMIVME-3111 control logic permits this to take place if the
board is operated in the interleaved (pipelined) mode. Operating requirements
for the interleaved
mode are discussed in Section 4. By eliminating T
1
, maximum throughput in
this mode is:
F
T
(maximum) = 53 kHz.
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