500-003111-000
3-8
3.4.4
Programmable Gain Amplifier
Voltage gain of the ADC channel is program-selectable as x1, x10,
x100, and x500. The gain may be changed between channel selections by
controlling
the two least significant bits (LSBs) (D00, D01) in the Gain Control Register
located at relative address 0E (HEX). When changing the gain, refer to Section
4.5.3 "Gain and Channel Selection Precedence" for proper software sequence.
3.5
FRONT PANEL (P3) ANALOG INPUTS
Sixteen single-ended, high-level, analog input channels are available
at the front panel through the P3 connector. By connecting the analog return in
the remote device to the INPUT GROUND SENSE input (Figure 3.5-1) in the P3
connector, the single-ended lines can be operated as pseudo-differential inputs.
3.5.1
P3 Low Pass Filters and Input Multiplexer
The 16 front panel analog inputs are available with low pass filters.
The outputs from the filters are then multiplexed into the analog configuration
network
for selection into the ADC channel. To achieve maximum system accuracy with
filtered analog inputs
, the sample rate should be limited to 300 Hz or less per
channel (4.8 kHz for 16 channels). Higher sample rates will produce reflected
"pumpback" currents at the inputs which can induce error voltages across the
filter input resistors.
Each of the P3 analog inputs is selected by the four LSBs (D00 to
D03) from the Control Register, these are shown as MUX A0 H through MUX A3
H in Figure 3.5-1. When set HIGH, CSR bit D07 selects the P3 multiplexer.
Channel "00" is routed through the self-test multiplexer before appearing at the
P3 multiplexer.
Signal pin assignments in the P3 connector are arranged for
cable-compatibility with the 3V and 5V series signal conditioner assemblies.
3.5.2
Current Loop Receiving Mode
P3 analog inputs may be used as current loop receivers by replacing
the filter capacitors with loop termination resistors. The resistance of the
terminators should be selected to produce a total termination power dissipation
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