500-003111-000
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3.7.2
Analog Configuration Network
The configuration networks are used to select the analog output
channels, or the self-test reference voltage, in addition to the P2 and P3 input
channels. The configuration networks are controlled by CSR control bits D08
through D10, shown in Figure 3.5-1 as MODE A0 H through MODE A2 H.
3.8 ANALOG
OUTPUTS
In addition to the 32 analog inputs, two analog outputs also are
available at the P2 connector. The analog outputs shown in Figure 3.8-1 are
derived from two dedicated 12-bit DACs which appear as two 16-bit registers in
the assigned VMIVME-3111 address space. Update rates for the output
channels are limited
only by the board access time and by the associated VME controller overhead.
3.8.1 DACs
Each DAC responds to the lower 12 bits of data in its WRITE-ONLY
Control Register (readback is not supported). Data is right-justified, and is
latched into the converter immediately when the register is updated. The two
converters share a common precision voltage reference which can be user-
configured for full-scale range, and for either bipolar or unipolar operation.
3.8.2
Output Buffers and Switches
Voltage levels from the DACs are buffered then switched to the P2
connector for routing through the system I/O cables. The output buffers are low
leakage, precision operational amplifiers which can supply 10 mA of drive
current over the full available output voltage range of ±10 V, and which can
withstand sustained short circuits to ground without damage.
Output switches permit the analog outputs to be disconnected from
P2 for "off-line" self-testing and for low impedance, single-point analog
input/output
system applications. To eliminate the effect of switch resistance on output
impedance, the inverting (sense) input of each output buffer is switched
between
the load and line side of the output switch for on-line and off-line operation.
Clamping diodes protect the buffers and switches from line transients by
preventing voltage excursions beyond the ±15 V supply rails.
Both outputs are monitored through the self-test multiplexer. By
monitoring the outputs at the sense inputs of the output buffers, the measured
output signals are correct in both the on-line and off-line operating modes.
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