500-003111-000
4-27
INTERRUPT LEVEL (Bits L2, L1, L0):
Determines the level at which an interrupt will occur:
REGISTER
BIT
L2 L1 L0
IRQ
LEVEL
0 0 0 DISABLED
0 0 1 IRQ1
0 1 0 IRQ2
0 1 1 IRQ3
1 0 0 IRQ4
1 0 1 IRQ5
1 1 0
IRQ6
1 1 1 IRQ7
INTERRUPT ENABLE (IRE, Bit 4):
When this bit is set HIGH, the bus interrupt associated with the Control
Register is enabled; the interrupt is disabled if IRE is LOW.
INTERRUPT AUTO-CLEAR (IRAC, Bit 3):
If the IRAC bit is set HIGH, the Interrupt Enable bit (IRE) is cleared during
the interrupt acknowledge cycle which responds to the request. The IRE
bit must then be set HIGH again to enable the interrupt.
EXTERNAL/INTERNAL (X/IN, Bit 5):
This control bit has no valid function on the VMIVME-3111 board and
MUST
be cleared LOW at all times.
FLAG ( F, Bit 7):
This control bit has no affect on the operation of the VMIVME-3111 board
and is available for use by the controlling processor as a utility flag.
FLAG AUTO-CLEAR (FAC, Bit 6):
If "FAC" is set HIGH, the flag bit "F" is automatically cleared during an
interrupt acknowledge cycle.
4.9.2
Interrupt Vector Register
Contents of the Interrupt Vector Register are supplied as a data byte
(D00 through D07) on the data bus during the board's INTERRUPT
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