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Digital Signal Processor (DSP)
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Digital Signal Processor (DSP)
The DSP is responsible for gathering data from the ADC and providing offset and
gain correction along with filtering. The DSP and the Erasable Programmable Logic
Device (EPLD) combine to control all board operations. During calibration, the DSP
collects up to seven different sets of data from user defined inputs. A least mean
square estimate of the channel transfer function is determined using this data. A gain
and offset coefficient for each channel is calculated from this estimate and stored
internally.
The data samples collected from the ADCs are corrected in real-time using the
calculated gain and offset coefficients. All DSP math operations are performed in
32-bit format, thereby preserving the high resolution provided by the ADCs. Output
data is truncated to 16 bits for consistency with reasonable limitations on linearity
within the input channel circuitry. The Firmware Revision Register contains the
current revision of the DSP code. A Watchdog Timer monitors the DSP to ensure the
code is processing normally. The DSP clears the Watchdog Timer every 30 msec. If for
some reason the DSP does not clear the timer, the timer times-out causing the
WDOG
bit
in the BCR to be set. This alerts the user of a problem and requires the user to software
reset the board through the BCR.
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