Fatal1ty H97 Killer Series
71
English
accessing columns within it.
Row Precharge Time (tRP)
he number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
he number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
he delay between when a memory chip is selected and when the irst active command can
be issued.
Write Recovery Time (tWR)
he amount of delay that must elapse ater the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
he number of clocks from a Refresh command until the irst Activate command to
the same rank.
RAS to RAS Delay (tRRD)
he number of clocks between two rows activated in diferent banks of the same
rank.
Write to Read Delay (tWTR)
he number of clocks between the last valid write operation and the next read
command to the same internal bank.
Read to Precharge (tRTP)
he number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
he time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Conigure CAS Write Latency.
