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How to Calculate the Capacitor of the Reset 

Input of a C51 Microcontroller

This application note explains how the reset of the 80C51 microcontroller works when
the RST pin is a pure input pin and when the RST input is bi-directional. It gives rules
to determine the extra components required to operate the reset function properly.
The reset process can be active on low or high level depending on the product. In this
application note only the high level case is discussed.

Introduction

The reset is used to start-up or to restart the 80C51 microcontroller activities. It forces
the 80C51 in a known state by reinitializing all the internal registers needed to properly
start the program execution. The reset must be kept active until all three of the follow-
ing conditions are respected:

The power supply must be in the specified range.

The oscillator must reach a minimum oscillation level to ensure a good noise to
signal ratio and a correct internal duty cycle generation.

The reset pulse width duration must be at least two machine cycles.

If one of the conditions is not respected the microcontroller will not startup properly. 

Theory of Reset Operation

To ensure a good startup, the reset pulse width has to be wide enough to cover the
period of time where the electrical conditions are not met. Two parameters should be
considered for a proper reset sequence to determine the reset pulse width (see
Figure 1):

t

osc

: time needed by the oscillator to reach the Vih1 or Vil1 level.

t

vddrise

: rise time of the power-supply taken between 10 to 90% of V

DD

.

When these two parameter conditions are met, the reset has to be maintained at least
two machine cycles in order to synchronize the internal activity of the core. In normal
mode, a machine cycle is 12-clock periods and in X2 mode is 6-clock periods.

Rev. 4284A–8051–09/03

80C51 

Microcontrollers

Application Note

Summary of Contents for 80C51

Page 1: ...ed range The oscillator must reach a minimum oscillation level to ensure a good noise to signal ratio and a correct internal duty cycle generation The reset pulse width duration must be at least two m...

Page 2: ...and Vil1 So the worst case condi tion is considered at the Vih1 level When the reset is released the program execution starts and the ALE signal toggles as it is illustrated in Figure 2 and showing a...

Page 3: ...ywhere in the program space except address 0000h Figure 3 If electrical Conditions are not Met the Reset Signal is Applied but without the Clock Reset is Released before VDD is Stable Figure 4 shows t...

Page 4: ...A pull down resistor Rrst is connected between the RST input and the ground An external capacitor Crst is con nected between the RST input and the VDD The value of Crst determines the reset time dura...

Page 5: ...in the next session Internal Reset In some cases such as a watchdog reset the microcontroller generates an internal reset by driving the rstcon signal and consequently by applying a high level on the...

Page 6: ...r supply has a finite transition time several hundreds of microsec onds to several milliseconds Crst is not so easy to compute by hand Excel tool is used to calculate Crst versus tvddrise and tosc par...

Page 7: ...ower Supply Voltage VDD 5 V Power Supply Rise Time 10 to 90 tvddrs 1 ms Oscillator Oscillator Startup Time time measured at VIH1 tosct 10 ms Electrical Characteristics of the Reset Input Minimum pull...

Page 8: ...9 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4...

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