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6

C51 Reset Guidelines

4284A–8051–09/03

Figure 7.  Reset Circuitry When an Internal Reset is Applied

Without Rrstext no external reset signal will be generated.

Use Excel File to 
Determine Crst

To determine Crst, the reset pulse width needs to be calculated using the following
equation:

treset = t

vddrise

 + t

osc

t

vddrise

 (typically 1 ms to 100 ms), is the rise time of the V

DD

 (10% and 90% of the 

V

DD

). It depends on the power supply and the decoupling capacitors used. 

t

osc

 (typically 1 ms to 50 ms), time taken by the oscillator at startup. It depends on 

the crystal characteristics and the capacitors connected to the crystal. 

Because the power supply has a finite transition time (several hundreds of microsec-
onds to several milliseconds), Crst is not so easy to compute by hand. Excel tool is
used to calculate Crst versus t

vddrise

 and t

osc

 parameters. A spreadsheet can be down-

loaded from the Atmel Web site to compute Crst

Four parameters have to be entered and Crst is directly computed by the spreadsheet
while 1k

 is chosen for Rrst. Here is how to do it:

V

DD

, the power supply voltage, is entered in the cell F3

t

vddrise

, the rise time of the power-supply, is entered in the cell F4

t

osc

, the oscillator startup time, is entered in cell F8

Rrstmin, the minimum pull-down resistor, is entered in the cell F13

After these steps, the cell E31 has to be clicked to compute the Crst and the minimum
reset pulse width.

0

VDD

0

Rrstwt

Rrst

Rrstext

Crst

Internal reset

V

DD

Vrst

Vih1

Summary of Contents for 80C51

Page 1: ...ed range The oscillator must reach a minimum oscillation level to ensure a good noise to signal ratio and a correct internal duty cycle generation The reset pulse width duration must be at least two m...

Page 2: ...and Vil1 So the worst case condi tion is considered at the Vih1 level When the reset is released the program execution starts and the ALE signal toggles as it is illustrated in Figure 2 and showing a...

Page 3: ...ywhere in the program space except address 0000h Figure 3 If electrical Conditions are not Met the Reset Signal is Applied but without the Clock Reset is Released before VDD is Stable Figure 4 shows t...

Page 4: ...A pull down resistor Rrst is connected between the RST input and the ground An external capacitor Crst is con nected between the RST input and the VDD The value of Crst determines the reset time dura...

Page 5: ...in the next session Internal Reset In some cases such as a watchdog reset the microcontroller generates an internal reset by driving the rstcon signal and consequently by applying a high level on the...

Page 6: ...r supply has a finite transition time several hundreds of microsec onds to several milliseconds Crst is not so easy to compute by hand Excel tool is used to calculate Crst versus tvddrise and tosc par...

Page 7: ...ower Supply Voltage VDD 5 V Power Supply Rise Time 10 to 90 tvddrs 1 ms Oscillator Oscillator Startup Time time measured at VIH1 tosct 10 ms Electrical Characteristics of the Reset Input Minimum pull...

Page 8: ...9 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4...

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