43
4317I–AVR–01/08
AT90PWM2/3/2B/3B
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. Only level interrupt.
8.5
Power Reduction Register
The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-
als to reduce power consumption. The current state of the peripheral is frozen and the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
A full predictible behaviour of a peripheral is not guaranteed during and after a cycle of stopping
and starting of its clock. So its recommended to stop a peripheral before stopping its clock with
PRR register.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
8.5.1
Power Reduction Register - PRR
• Bit 7 - PRPSC2: Power Reduction PSC2
Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this
module. When waking up the PSC2 again, the PSC2 should be re initialized to ensure proper
operation.
• Bit 6 - PRPSC1: Power Reduction PSC1
Table 8-2.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillator
s
Wake-up Sources
Sleep
Mode
cl
k
CPU
cl
k
FLASH
cl
k
IO
cl
k
ADC
cl
k
PLL
Ma
in
Clo
c
k
Sour
ce Enab
led
INT3
..0
PSC
SPM
/EEPROM
R
e
ady
ADC
WDT
O
ther
I/O
Idle
X
X
X
X
X
X
X
X
X
X
ADC
Noise
Reduction
X
X
X
X
X
X
X
X
Power-
down
X
X
X
Standby
X
X
X
Bit
7
6
5
4
3
2
1
0
PRPSC2
PRPSC1
PRPSC0
PRTIM1
PRTIM0
PRSPI
PRUSART
PRADC
PRR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
