128
2467S–AVR–07/09
ATmega128
Figure 53.
Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the compare registers. If the TOP value is lower than any of the com-
pare registers, a compare match will never occur between the TCNTn and the OCRnx. Note that
when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Reg-
isters are written. As the third period shown in
illustrates, changing the TOP actively
while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical
output. The reason for this can be found in the time of update of the OCRnx Register. Since the
OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the
length of the falling slope is determined by the previous TOP value, while the length of the rising
slope is determined by the new TOP value. When these two values differ the two slopes of the
period will differ in length. The difference in length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx1:0 to 3 (See
). The
actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis-
ter at the compare match between OCRnx and TCNTn when the counter increments, and
clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when
OCRnx / TOP Update
and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
2
3
4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
