299
2467S–AVR–07/09
ATmega128
Figure 142.
Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
The timing requirements shown in
(i.e. t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading
operation.
Figure 143.
Parallel Programming Timing, Reading Sequence (Within the Same Page) with
Timing Requirements
Note:
The timing requirements shown in
(i.e. t
DVXH
, t
XHXL
, and t
XLDX
) also apply to reading
operation.
Table 126.
Parallel Programming Characteristics, V
CC
= 5 V ± 10%
Symbol
Parameter
Min
Typ
Max
Units
V
PP
Programming Enable Voltage
11.5
12.5
V
I
PP
Programming Enable Current
250
μ
A
t
DVXH
Data and Control Valid before XTAL1 High
67
ns
t
XLXH
XTAL1 Low to XTAL1 High
200
ns
t
XHXL
XTAL1 Pulse Width High
150
ns
t
XLDX
Data and Control Hold after XTAL1 Low
67
ns
t
XLWL
XTAL1 Low to WR Low
0
ns
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BHDV
t
OLDV
t
XLOL
t
OHDZ
