322
2467S–AVR–07/09
ATmega128
Two-wire Serial Interface Characteristics
describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
.
Notes:
1. In ATmega128, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100 kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
Table 133.
Two-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
V
IL
Input Low-voltage
-0.5
0.3 V
CC
V
V
IH
Input High-voltage
0.7 V
CC
V
CC
+ 0.5
V
V
hys
Hysteresis of Schmitt Trigger Inputs
0.05 V
CC
–
V
V
Output Low-voltage
3 mA sink current
0
0.4
V
t
r
Rise Time for both SDA and SCL
20 + 0.1C
b
300
ns
t
of
Output Fall Time from V
IHmin
to V
ILmax
10 pF < C
b
< 400 pF
20 + 0.1C
b
250
ns
t
Spikes Suppressed by Input Filter
0
50
ns
I
i
Input Current each I/O Pin
0.1 V
CC
< V
i
< 0.9 V
CC
-10
10
µA
C
i
Capacitance for each I/O Pin
–
10
pF
f
SCL
SCL Clock Frequency
f
CK
> max(16f
SCL
, 250kHz)
0
400
kHz
Rp
Value of Pull-up resistor
f
SCL
≤
100 kHz
f
SCL
> 100 kHz
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤
100 kHz
4.0
–
µs
f
SCL
> 100 kHz
0.6
–
µs
t
LOW
Low Period of the SCL Clock
f
SCL
≤
100 kHz
4.7
–
µs
f
SCL
> 100 kHz
1.3
–
µs
t
HIGH
High period of the SCL clock
f
SCL
≤
100 kHz
4.0
–
µs
f
SCL
> 100 kHz
0.6
–
µs
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤
100 kHz
4.7
–
µs
f
SCL
> 100 kHz
0.6
–
µs
t
HD;DAT
Data hold time
f
SCL
≤
100 kHz
0
3.45
µs
f
SCL
> 100 kHz
0
0.9
µs
t
SU;DAT
Data setup time
f
SCL
≤
100 kHz
250
–
ns
f
SCL
> 100 kHz
100
–
ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤
100 kHz
4.0
–
µs
f
SCL
> 100 kHz
0.6
–
µs
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤
100 kHz
4.7
–
µs
V
CC
0,4V
–
3mA
----------------------------
1000ns
C
b
-------------------
Ω
V
CC
0,4V
–
3mA
----------------------------
300ns
C
b
----------------
Ω
