259
2467S–AVR–07/09
ATmega128
Figure 128.
Boundary-scan Cells for Oscillators and Clock Options
summaries the scan registers for the external clock pin XTAL1, oscillators with
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Notes:
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported
in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-
nal capacitors to run unless the fuse is correctly programmed.
Scanning the Analog
Comparator
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
is attached to each of these signals. The signals are
described in
.
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Table 102.
Scan Signals for the Oscillators
Enable signal
Scanned Clock
Line
Clock Option
Scanned Clock Line
when not Used
EXTCLKEN
EXTCLK (XTAL1)
External Clock
0
OSCON
OSCCK
External Crystal
External Ceramic Resonator
0
RCOSCEN
RCCK
External RC
1
OSC32EN
OSC32CK
Low Freq. External Crystal
0
TOSKON
TOSCK
32 kHz Timer Oscillator
0
0
1
D
Q
From
Previous
Cell
ClockDR
ShiftDR
To
next
cell
To System Logic
FF1
0
1
D
Q
D
Q
G
0
1
From
Previous
Cell
ClockDR
UpdateDR
ShiftDR
To
Next
Cell
EXTEST
From Digital Logic
XTAL1/TOSC1
XTAL2/TOSC2
Oscillator
ENABLE
OUTPUT
