APx PDM 16 Input Module for B Series: Specifications
77
PDM 16
PDM Input Jitter Tolerance
Sine wave jitter, bit clock rates from 128kHz
to 24.576 MHz
<= 3.5 UI (sub-
ject to 1591ns
max jitter limit)
UI
2
Notes to Specifications
1. System specification including contributions from both generator and analyzer subject to the following condition: Bit Clock
≥
192 kHz.
2. For PDM, the Unit Interval (UI) is defined as 1/fb, where fb is the bitclock rate in hertz.
Parameter
Symbol
Test Conditions
Min
Type
Max
Unit
Summary of Contents for APx555
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Page 32: ...30 Abbreviations Terms and Symbols ...
Page 56: ...54 APx ADIO Module for B Series Specifications ADIO ...
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