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30-Oct-2020, Rev. 1.1

24

2.8.2

Voltage Regulators

The following table lists the power solution for the IO Carrier Card. Two rails are
independent and adjustable supplying power to the Zynq PL I/O banks and connected
Pmods™. VCCio_35 drives banks 35 and 13 (if 7Z020 is populated on MicroZed) as
well as 5 Pmod™ connectors.

The table below shows the minimum required voltage rails, currents, and tolerances.

Table 20 – Voltage Rails w/ Current Estimates

Voltage (V)

7Z010

Current

7Z020

Current

Tolerance

IC

Notes

Vin (MicroZed Module)

5W

6.5W

5.00%

N/A

Filtered from

Vin, J4.3

Vadj (VCCio_34) – 1.8V,
2.5V or 3.3V

2.3A @ 3.3V

2.3A @ 3.3V

5.00%

REG3,

MAX15066

Pmods +

VCCio

Banks, TP8

Vadj (VCCio_35) – 1.8V,
2.5V or 3.3V

<2.0A @ 3.3V

2.85A @ 3.3V

5.00%

REG4,

MAX15066

Pmods +

VCCio

Banks, TP9

1.8 (analog/Vccadc)

150 mA

150 mA

5.00%

REG1, MAX8891-

18

Filtered from

Vin, TP6

1.25V (analog/Vref)

50 mA

50 mA

0.2%

REG2,

MAX6037A-12

Filtered from

Vin, TP7

3.3V Main

490 mA

500 mA

5.00%

REG5,

MAX17

Filtered from

Vin, TP10

5.0V (analog/AMS)

0.15A

0.15A

5.00%

N/A

Filtered from

Vin, Top of

C36

2.8.3

Sequencing

•

PWR_EN signal, active high, JX1.5, allows the carrier to turn on or off the
MicroZed power supplies. R81 and C93 have been placed to facilitate the
timing of this signal during power off conditions. This signal should not be de-
asserted until VCCIO_EN is de-asserted. In the carrier off condition (power
plug removed or power switch turned off), this signal is driven low by the carrier
board.

•

VCCIO_EN signal, active high, JX2.10, originates on the microZed and is the
output of the 1.8V regulator, PG_1V8. This signal enables the carrier’s 3.3V
supply, which in turn enables both VCCIO_34 and VCCIO_13/35. When the
carrier is turned off (power switch turned off or power plug removed) or the
MicroZed’s PG_1V8 signal is de-asserted VCCI_EN is driven low, which turns
off the IOCC and the MicroZed.

•

PG_CARRIER signal, active high, JX2.11, is pulled up by MicroZed’s +3.3V
PG_MODULE signal. This signal is pulled low by the carrier board or the
MicroZed when either board’s power circuitry is not ‘Good’ yet.

•

The following diagram illustrates the power supply sequencing on power up.
Note Vin and PWR_Enable can come up simultaneously, but shown staggered
as PWR_Enable can come up later.

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Summary of Contents for MicroZed

Page 1: ...MicroZed I O Carrier Card Zynq System On Module Hardware User Guide Revision 1 1 30 Oct 2020 ...

Page 2: ...h Buttons 8 2 4 2 User LEDs 8 2 4 3 DIP Switches 8 2 5 INTERFACE HEADERS 9 2 5 1 Digilent Pmod Compatible Expansion Headers 2x6 9 2 5 2 JX1 and JX2 MicroZed interface microheaders 13 2 6 AGILE MIXED SIGNALING AMS INTERFACE 19 2 6 1 XADC alternate GPIO function 20 2 7 JTAG CONFIGURATION 22 2 8 POWER 23 2 8 1 Power Input 23 2 8 2 Voltage Regulators 24 2 8 3 Sequencing 24 2 8 4 Bypassing Decoupling 2...

Page 3: ...ible interfaces One connected to PS MIO Two connected to Bank 13 PL MicroZed with Zynq 7Z020 only Five connected to Bank 34 PL Four connected to Bank 35 PL o Two 100 pin MicroHeaders o Reset Push Button o 4 User Push Buttons o 2 Configuration Push Buttons o 8 User LEDs o 4 User DIP Switches o 2 Status LEDs o Xilinx XADC Header On board Oscillator o 100MHz single ended with FPGA control On board Me...

Page 4: ...d 5 Bank 34 1 Bank 13 1 32 8 7 Pmod Pmod Pmod Pmod 6 Pmod 4 Bank 35 1 Bank 13 PS Pmod 1 PUDC PWR_Enable 4 Pushbuttons BTN 4 4 DIP Switches 4 PG_Carrier POR BTN 1 Init_B BTN Pmod Bank 13 Pmod only has 7 I O Pins 100 MHz 8 Bank 0 pins Bank 34 35 pins Power Pins 8 8 User LEDs Control 1 Optional SHA Security EEPROM 1Kb Vccio_en 1 1 1 4 5 1 1 VBAT 1 Figure 1 MicroZed IOCC Block Diagram ...

Page 5: ...30 Oct 2020 Rev 1 1 4 Figure 2 IOCC Topology ...

Page 6: ...ignments The following figure shows the Zynq bank pin assignments on the MicroZed followed by a table that shows the detailed I O connections See tables Table 12 JX1 Connections and Table 13 JX2 Connections Figure 3 Zynq CLG400 Bank Assignments ...

Page 7: ...actory installed into the chip The DS28E02 communicates over the single contact 1 Wire bus The communication follows the standard 1 Wire protocol with the registration number acting as the node address in the case of a multidevice 1 Wire network Pin 2 of this device must be pulled high with a 680ohm resistor to VCCio_34 Table 1 SHA EEPROM Connection Carrier Net Name MicroHeader Connection Zynq AP ...

Page 8: ...onnection Carrier Net Name MicroHeader Connection Zynq AP SOC Connection PG_CARRIER JX2 11 PG_MODULE 2 3 3 Processor Subsystem Reset SYS_RST button SW4 The SYS_RST button provides and active low signal to net CARRIER_SRST which allows the user to reset all of the functional logic within the device without disturbing the debug environment For example the previous break points set by the user remain...

Page 9: ...nt limiting resistors Note if VCCio_34 is set to 1 8V the LED intensity will be noticeably lower than when VCCio_34 is set to 3 3V Table 7 LED Connections Carrier Net Name MicroHeader Connection Zynq AP SOC Connection LED0 JX1 pin 41 Bank 34 U14 LED1 JX1 pin 43 Bank 34 U15 LED2 JX1 pin 42 Bank 34 U18 LED3 JX1 pin 44 Bank 34 U19 LED4 JX1 pin 9 Bank 34 R19 LED5 JX1 pin 19 Bank 34 V13 LED6 JX1 pin 24...

Page 10: ...e to one another to ensure high speed signal integrity The Digilent Pmod compatible interface connects to Zynq banks 500 34 35 and 13 Bank 13 is only available on the 7Z020 version MicroZed The PS Pmod attached to bank 500 can be used for PJTAG access MIO 10 13 as well as utilizing nine other hardened MIO peripherals SPI GPIO CAN I2C UART SD QSPI Trace Watchdog NOTE The PS Pmod is also accessible ...

Page 11: ... Pin 9 JX1 pin 23 Bank 34 T14 JA6 7 N Pin 10 JX1 pin 25 Bank 34 T15 Pmod Carrier Net Name Pmod Pin Number MicroHeader Connection Zynq AP SOC Connection JB Pmod JB0 1 P Pin 1 JX1 pin 29 Bank 34 Y16 JB0 1 N Pin 2 JX1 pin 31 Bank 34 Y17 JB2 3 P Pin 3 JX1 pin 30 Bank 34 W14 JB2 3 N Pin 4 JX1 pin 32 Bank 34 Y14 JB4 5 P Pin 7 JX1 pin 35 Bank 34 T16 JB4 5 N Pin 8 JX1 pin 37 Bank 34 U17 JB6 7 P Pin 9 JX1 ...

Page 12: ...eader Connection Zynq AP SOC Connection JF Pmod JF0 1 P Pin 1 JX2 pin 35 Bank 35 M19 JF0 1 N Pin 2 JX2 pin 37 Bank 35 M20 JF2 3 P Pin 3 JX2 pin 36 Bank 35 M17 JF2 3 N Pin 4 JX2 pin 38 Bank 35 M18 JF4 5 P Pin 7 JX2 pin 41 Bank 35 L19 JF4 5 N Pin 8 JX2 pin 43 Bank 35 L20 JF6 7 P Pin 9 JX2 pin 42 Bank 35 K19 JF6 7 N Pin 10 JX2 pin 44 Bank 35 J19 Pmod Carrier Net Name Pmod Pin Number MicroHeader Conne...

Page 13: ...in 7 JX1 pin 91 Bank 13 V8 JY4 5 N Pin 8 JX1 pin 93 Bank 13 W8 JY6 7 P Pin 9 JX1 pin 92 Bank 13 T5 JY6 7 N Pin 10 JX1 pin 94 Bank 13 U5 Pmod Carrier Net Name Pmod Pin Number MicroHeader Connection Zynq AP SOC Connection JZ Pmod JZ0 1 P Pin 1 JX2 pin 93 Bank 13 Y12 JZ0 1 N Pin 2 JX2 pin 95 Bank 13 Y13 JZ2 3 P Pin 3 JX2 pin 94 Bank 13 V11 JZ2 3 N Pin 4 JX2 pin 96 Bank 13 V10 JZ4 5 P Pin 7 N C JZ4 5 ...

Page 14: ...Zed does not power the PL VCCIO banks this is required by the Carrier This gives the Carrier the flexibility to control the I O bank voltages The 7Z010 has two PL I O banks banks 34 and 35 each containing 50 I O The 7Z020 has a third I O bank bank 13 which is powered on the IOCC by the same supply as Bank35 Within a PL I O bank there are 50 I O capable of 24 differential pairs Differential LVDS pa...

Page 15: ...assignments Table 11 MicroHeader Pinout MicroHeader 1 MicroHeader 2 Signal Name Source Pin Count Signal Name Source Pin Count PL All Bank 34 Pins Zynq Bank 34 49 PL All Bank 35 Pins Zynq Bank 35 50 JTAG TMS_0 Zynq Bank 0 5 P S PS Pmod MIO 0 9 15 Zynq Bank 500 8 TDI_0 Zynq Bank 0 TCK_0 Zynq Bank 0 C Init_B_0 Zynq Bank 0 2 TDO_0 Zynq Bank 0 Program_B_0 Zynq Bank 0 Carrier_SRST Carrier Power PG_Modul...

Page 16: ...nk 34 T16 IO_L9P_T1_DQS_34 Pmod JB pin 7 JB4 5 N JX1 pin 37 Bank 34 U17 IO_L9N_T1_DQS_34 Pmod JB pin 8 JB6 7 P JX1 pin 36 Bank 34 V15 IO_L10P_T1_34 Pmod JB pin 10 JB6 7 N JX1 pin 38 Bank 34 W15 IO_L10N_T1_34 Pmod JC pin 1 JC0 1 P JX1 pin 47 Bank 34 N18 IO_L13P_T2_MRCC_34 Pmod JC pin 2 JC0 1 N JX1 pin 49 Bank 34 P19 IO_L13N_T2_MRCC_34 Pmod JC pin 3 JC2 3 P JX1 pin 48 Bank 34 N20 IO_L14P_T2_SRCC_34 ...

Page 17: ...C pin 8 XADC_AD8_P JX2 pin 18 Bank 35 B19 IO_L1P_T0_AD8P_35 XADC pin 7 XADC_AD8_N JX2 pin 20 Bank 35 A20 IO_L1N_T0_AD8N_35 XADC pin 17 XADC_GIO1 JX2 pin 13 Bank 35 G14 IO_0_35 XADC pin 18 XADC_GIO0 JX2 pin 47 Bank 35 L16 IO_L11P_T1_SRCC_35 XADC pin 19 XADC_GIO3 JX2 pin 49 Bank 35 L17 IO_L11N_T1_SRCC_35 XADC pin 20 XADC_GIO2 JX2 pin 14 Bank 35 J15 IO_25_35 Pmod JE pin 1 JE0 1 P JX2 pin 23 Bank 35 E...

Page 18: ...90 Bank 35 J16 IO_L24N_T3_AD15N_35 PB pin 3 PB0 JX2 pin 68 Bank 35 J20 IO_L17P_T2_AD5P_35 PB pin 3 PB1 JX2 pin 70 Bank 35 H20 IO_L17N_T2_AD5N_35 PB pin 3 PB2 JX2 pin 67 Bank 35 G19 IO_L18P_T2_AD13P_35 PB pin 3 PB3 JX2 pin 69 Bank 35 G20 IO_L18N_T2_AD13N_35 BB_CLK_P BB_CLK_P JX2 pin 48 Bank 35 K17 IO_L12P_T1_MRCC_35 BB_CLK_P BB_CLK_P JX2 pin 50 Bank 35 K18 IO_L12N_T1_MRCC_35 PG_CARRIER PG_CARRIER J...

Page 19: ...s by putting them at the end of the connector with a GND isolating them from other signals To minimize noise coupling the auxiliary multi use analog signals IO_L P_T1_AD P N_ use layer isolation pair routing and distance separation from other signals Some of these are shared with DQ byte groups above in these cases the DQ routing is more important Table 14 Data Byte Grouping Byte Group Zynq Pins B...

Page 20: ...on between channels The plug in cards which will facilitate a number of reference designs have not yet been designed so this pin out must provide a reasonable degree of freedom while also keeping resource requirements as minimal as possible The Carrier AMS header is comparable with similar connectors on the Xilinx KC705 and ZC702 boards Any AMS plug in cards built for those boards should be compat...

Page 21: ...igital GPIO functionality Table 15 XADC alternate GPIO table Carrier Connection Carrier Net Name MicroHeader Connection Zynq AP SOC Connection Zynq AP SOC Pin XADC pin 3 XADC_AD0_P JX2 pin 17 Bank 35 C20 IO_L1P_T0_AD0P_35 XADC pin 4 XADC_AD0_N JX2 pin 19 Bank 35 B20 IO_L1N_T0_AD0N_35 XADC pin 3 XADC_AD0_P JX2 pin 18 Bank 35 B19 IO_L1P_T0_AD8P_35 XADC pin 4 XADC_AD0_N JX2 pin 20 Bank 35 A20 IO_L1N_...

Page 22: ...X8N Two pins required Auxiliary analog input channel 8 Two dedicated channels needed for simultaneous sampling applications Should also support use as IO inputs by disconnection of anti alias cap see 1V peak to peak input maximum 7 8 XADC AD8N R D17 XADC AD8P R D16 DXP DXN Two pins required Access to thermal Diode 12 9 XADC DXN N12 XADC DXP N11 AGND Three pins required Analog ground reference GNDA...

Page 23: ...PUDC_B Connections Carrier Net Name MicroHeader Connection Zynq AP SOC Connection Zynq AP SOC Pin PUDC JX1 pin 17 Bank 34 U13 IO_L3P_T0_DQS_PUDC_B_34 A blue DONE LED is connected to Zynq through the MicroHeader When the PL is properly configured the DONE LED will light Table 18 Done Connections Carrier Net Name MicroHeader Connection Zynq AP SOC Connection Zynq AP SOC Pin FPGA_DONE JX1 pin 8 Bank ...

Page 24: ...O equates to a max current of 1 056A 3 3V The PMOD power connections are capable of sourcing 3 3V at 100mA each The precise current demand is based on the end use I O requirements and therefore the application will determine the minimum current a power supply must source As shipped from Avnet a 5V 2 Amp or larger power supply is provided in the kit o Barrel Jack Input 5V 2A Barrel Jack 2 5mm inner...

Page 25: ...ltered from Vin Top of C36 2 8 3 Sequencing PWR_EN signal active high JX1 5 allows the carrier to turn on or off the MicroZed power supplies R81 and C93 have been placed to facilitate the timing of this signal during power off conditions This signal should not be de asserted until VCCIO_EN is de asserted In the carrier off condition power plug removed or power switch turned off this signal is driv...

Page 26: ...il Zynq s core power is valid The PG_CARRIER on IOCC and PG_MODULE on MicroZed signals are wired OR and tied to the Zynq Power On Reset signal When the power supplies are valid on both the SOM and carrier the PG signal de asserts the Zynq POR signal 2 8 4 Bypassing Decoupling The IOCC follows the recommended decoupling techniques per each manufacturer s datasheet 2 8 5 System Power Good LED A gree...

Page 27: ...a MicroZed inserted DIP_SW0 3 DIP_SWx In low position 4 user slide switches to the Zynq PL fabric Pulled low Active when high SW2 POR Open Active low Power On Reset signal See section 2 3 2 SW3 INIT Open Active low initialization signal Rarely used See section 2 3 1 SW4 CARRIER_SRST Open Active low FPGA PS reset Interfaced with JTAG J2 See section 2 3 3 TP1 CARRIER_SRST N A Signal monitor test poi...

Page 28: ... Oct 2020 Rev 1 1 27 3 Mechanical 3 1 Dimensions Figure 10 IOCC Horizontal Mechanical Dimensions mils Figure 11 Total height from Bumper to Switch top 20 00 mm Figure 12 Switch Height no bumpers 18 00 mm ...

Page 29: ...with rubber feet and all jumpers populated is 110 grams 3 8801 oZ 4 Revision History Rev date Rev Reason for change 27 Dec 13 1 0 Updated graphics and power section Updated tables based on review feedback Updated power section photos diagram based on new data and review feedback 30 Oct 20 1 1 Corrected barrel jack ...

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