MSC SM2S-IMX8M User Manual
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4.8 SPI Bus
The i.MX8M SMARC module offers two Enhanced Configurable SPI (ECSPI) busses with two slave select signals each.
Key features of the ECSPI include:
•
Full-duplex synchronous serial interface
•
Two Chip Select (CS) signals to support multiple peripherals
•
Transfer continuation function allows unlimited length data transfers
•
32-bit wide by 64-entry FIFO for both transmit and receive data
•
Polarity and phase of the Chip Select (CS) and SPI Clock (SCLK) are configurable
•
Direct Memory Access (DMA) support
Table 4-8: SPI Signal Description
Signal
Pin Type
Signal
Level
Pin on
i.MX8M
Pin name on
i.MX8M
Power
Tolerance
PU/PD
Description
SPI0_DIN
I
1.8V CMOS
B5
ECSPI2_MISO
1.8V
Master Input Slave Output
SPI0_DO
O PP
1.8V CMOS
E5
ECSPI2_MOSI
1.8V
Master Output Slave Input
SPI0_CK
O PP
1.8V CMOS
C5
ECSPI2_SCLK
1.8V
Clock Output
SPI0_CS0#
O PP
1.8V CMOS
J22
NAND_DATA05 1.8V
PU 10k 1.8V
Chip-Select0, available for baseboard usage
(GPIO3_IO11)
SPI0_CS1#
O PP
1.8V CMOS
K1
SAI1_RXC
1.8V
PU 10k 1.8V
Chip-Select1, available for baseboard usage
(GPIO4_IO01)
SPI1_DIN
I
1.8V CMOS
B4
ECSPI1_MISO
1.8V
Master Input Slave Output
SPI1_DO
O PP
1.8V CMOS
A4
ECSPI1_MOSI
1.8V
Master Output Slave Input
SPI1_CK
O PP
1.8V CMOS
D5
ECSPI1_SCLK
1.8V
Clock Output
SPI1_CS0#
O PP
1.8V CMOS
L20
NAND_DATA04 1.8V
PU 10k 1.8V
Chip-Select 0, available for baseboard usage
(GPIO3_IO10)
SPI1_CS1#
O PP
1.8V CMOS
J1
SAI1_RXD4
1.8V
PU 10k 1.8V
Chip-Select 1, available for baseboard usage
(GPIO4_IO06)
NOTE:
GPIOs are used for chip select pins SPI[0:1]_CS[0:1]#.
In case SPI1 is implemented, only SER[0:2] are available.
