X20 system modules • Digital mixed modules • X20DM9324
1060
X20 system User's Manual 3.10
4.14.2.10 Register description
4.14.2.10.1 Function model 0 - Standard
Read
Write
Register
Fixed offset Name
Data type
Cyclic
Acyclic
Cyclic
Acyclic
USINT
DigitalInput01
Bit 0
...
...
0
1
DigitalInput08
Bit 7
●
DigitalOutput
DigitalOutput01
Bit 0
...
...
2
0
DigitalOutput04
Bit 3
●
18
-
USINT
●
USINT
StatusDigitalOutput01
Bit 0
...
30
2
StatusDigitalOutput04
Bit 3
●
Fixed modules require their data points to be in a specific order in the X2X frame. Cyclic access occurs according
to a predefined offset, not based on the register address.
Acyclic access is continues to be based on the register numbers.
4.14.2.10.2 Function model 254 - Bus controller
Read
Write
Register
Offset
1)
Name
Data type
Cyclic
Acyclic
Cyclic
Acyclic
Input state of digital inputs 1 to 8
USINT
DigitalInput01
Bit 0
...
...
0
0
DigitalInput08
Bit 7
●
Switching state of digital outputs 1 to 4
DigitalOutput01
Bit 0
...
...
2
0
DigitalOutput04
Bit 3
●
18
-
USINT
●
Status of digital outputs 1 to 4
USINT
StatusDigitalOutput01
Bit 0
...
30
-
StatusDigitalOutput04
Bit 3
●
1)
The offset specifies where the register is within the CAN object.
4.14.2.10.3 Digital inputs
Unfiltered
The input state is collected with a fixed offset to the network cycle and transferred in the same cycle.
Filtered
The filtered status is collected with a fixed offset to the network cycle and transferred in the same cycle. Filtering
takes place asynchronously to the network in multiples of 200 µs with a network-related jitter of up to 50 µs.
Summary of Contents for X20 System
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