X20 system modules • Analog input modules • X20AP31x1
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X20 system User's Manual 3.10
Transmitting and receiving with Forward
The basic algorithm for transmitting and receiving data remains the same. With the Forward function, up to seven
unacknowledged sequences can be transmitted. Sequences can be transmitted without having to wait for the
previous message to be acknowledged. Since the delay between writing and response is eliminated, a considerable
amount of additional data can be transferred in the same time window.
Algorithm for transmitting
Cyclic status query:
- The Module monitors the OutputSequenceCounter.
0) Cyclic checks:
- The CPU must check OutputSyncAck.
→ If OutputSyncAck = 0: Reset the OutputSyncBit and resynchronize the channel.
- The CPU must check whether OutputMTU is enabled.
→ If OutputSequenceCounter > OutputSeque 7, then it is not enabled because the last sequence has not yet been acknowledged.
1) Preparation (create transmit array):
- The CPU must split up the message into valid segments and create the necessary control bytes.
- The CPU must add the segments and control bytes to the transmit array.
2) Transmit:
- The CPU must transfer the current part of the transmit array to the OutputMTU.
- The CPU must increase the OutputSequenceCounter for the sequence to be accepted by the module.
- The CPU can then
transmit
in the next bus cycle if the MTU has been enabled.
The module responds since OutputSequenceCounter > OutputSequenceAck:
- The module accepts data from the internal receive buffer and appends it to the end of the internal receive array.
- The module is acknowledged and the currently received value of the OutputSequenceCounter is transferred to OutputSequenceAck.
- The module requests the status cyclically again.
3) Completion (acknowledgment):
- The CPU must check OutputSequenceAck cyclically.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via OutputSequenceAck. In order to detect potential trans-
mission errors in the last sequence as well, it is important to make sure that the algorithm is run through long enough.
Note:
To monitor communication times exactly, the task cycles that have passed since the last increase of the OutputSequenceCounter should be counted. In this
way, the number of previous bus cycles necessary for the transmission can be measured. If the monitoring counter exceeds a predefined threshold, then the
sequence can be considered lost (the relationship of bus to task cycle can be influenced by the user so that the threshold value needs to be determined individ-
ually).
Algorithm for receiving
0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks if InputMTU is enabled.
→ Enabling criteria: InputSequenceCounter > InputSeque Forward
Preparation:
- The module forms the control bytes / segments and creates the transmit array.
Action:
- The module transmits the current part of the transmit array to the receive buffer.
- The module increases the InputSequenceCounter.
- The module waits for a new bus cycle after the ForwardDelay time has expired.
- The module repeats the action if the InputMTU is enabled.
1) Receiving (InputSequenceCounter > InputSequenceAck):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
Summary of Contents for X20 System
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