X20 system modules • Counter modules • X20DC1178
X20 system User's Manual 3.10
683
4.11.4.9.4.8 Status of signal lines
Name:
BW_Channel_D
This register displays the error state of the signal line from the encoder. The error state is latched when it occurs
and is maintained until acknowledged. The counter and time registers are not updated if there are pending or
unacknowledged errors.
Data type
Value
USINT
See bit structure.
Bit structure:
Bit
Name
Value
Information
0
No error - Encoder signal D
0
BW_Channel_D
1
Error status - Open line or short circuit (voltage level too low)
1 - 7
Reserved
0
4.11.4.9.4.9 Acknowledging error status of the signal line
Name:
BW_QuitChannel_D
This register can be used to acknowledge the latched error states of the signal lines from the encoder. However,
if there are still pending errors remaining, then the error status remains active. After acknowledging the errors, the
bit must also be reset or else any repetition of the error will be undetected.
Data type
Value
USINT
See bit structure.
Bit structure:
Bit
Name
Value
Information
0
No acknowledgment
0
BW_QuitChannel_D
1
Acknowledgment of error status
1 - 7
Reserved
0
4.11.4.9.4.10 Status of encoder supplies
Name:
PowerSupply01 to PowerSupply02
This register shows the status of the integrated encoder supplies. A faulty encoder power supply is displayed as
a warning.
Data type
Value
USINT
See bit structure.
Bit structure:
Bit
Name
Value
Information
0
24 VDC encoder power supply OK
0
PowerSupply01
1
24 VDC encoder power supply faulty
0
5 VDC encoder power supply OK
1
PowerSupply02
1
5 VDC encoder power supply faulty
2 - 7
Reserved
-
4.11.4.9.5 Minimum cycle time
The minimum cycle time defines how far the bus cycle can be reduced without causing a communication error
or impaired functionality. It should be noted that very fast cycles decrease the idle time available for handling
monitoring, diagnostics and acyclic commands.
Minimum cycle time
150 µs
4.11.4.9.6 Minimum I/O update time
The minimum I/O update time defines how far the bus cycle can be reduced while still allowing an I/O update to
take place in each cycle.
Minimum I/O update time
150 µs
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