Basler L301kc Installation And Operating Manual Download

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Camera Interface

Basler L301kc

2-13

DRAFT

Operation in 60 MHz Single Pixel 10 Bit Mode or Single Pixel 8 Bit Mode

In 60 MHz Single Pixel 10 Bit mode, the pixel clock operates at 60 MHz. On each clock cycle, the
camera transmits data for one pixel at 10 bit depth and a line valid bit. The assignment of the bits
is shown in Table 2-3.

The pixel clock is used to time data sampling and transmission. As shown in Figure 2-6 and Figure
2-7, the

L301

samples and transmits data on each falling edge of the pixel clock.

The line valid bit indicates that a valid line is being transmitted. Pixel data is only valid when this
bit is high.

Operation in 60 MHz Single Pixel 8 Bit mode is similar to 10 bit mode except that the two least
significant bits output from each ADC are dropped and only 8 bits of data per pixel is transmitted.

Video Data Sequence

When the camera is not transmitting valid data, the line valid bit sent on each cycle of the pixel
clock will be low. Once the camera has completed line acquisition, it will begin to send valid data:

• On the pixel clock cycle where valid line data transmission begins, the line valid bit will

become high. Ten of the bits transmitted during this clock cycle will contain the data for pixel
number one in the red line.

• On the second cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmit-

ted during this clock cycle will contain the data for pixel number one in the green line.

• On the third cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted

during this clock cycle will contain the data for pixel number one in the blue line.

• On the fourth cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted

during this clock cycle will contain the data for pixel number two in the red line.

• On the fifth cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted

during this clock cycle will contain the data for pixel number two in the green line.

• On the sixth cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted

during this clock cycle will contain the data for pixel number two in the blue line.

• This pattern will continue for 6294 cycles of the pixel clock. (The camera must transmit data

for 2098 pixels in each line and there are three lines; 3 x 2098 = 6294.)

• After the data for all 6294 pixels has been transmitted, the line valid bit will become low indi-

cating that valid line data is no longer being transmitted.

Figure 2-6 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode. Figure 2-7 shows the data sequence when the camera is operating in
programmable exposure mode.

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The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.

The data sequence outlined below, along with Figure 2-6 and Figure 2-7, describe
what is happening at the inputs to the Camera Link transmitter in the camera.

Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.