SiI
164
PanelLink
Transmitter
Data Sheet
Functional Description
The
SiI
164 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 24 bits for data Input to
allow for panel support up to UXGA resolution. Figure 2 shows the functional blocks of the chip.
Registers
&
Configuration
Logic Block
SCL
SDA
PD
EDGE/HTPLG
BSEL/SCL
DSEL/SDA
CTL/A/DK[3:1]
I
2
C
Slave
Machine
Data Capture
Logic Block
D[23:0]
IDCK+
IDCK-
VSYNC
HSYNC
TXC
+
TX0
+
TX1
+
TX2
+
VREF
DE
MSEN
PanelLink
PanelLink
PanelLink
PanelLink
Digital
core
ISEL/RST
EXT_SWING
DKEN
A[3:1]
Figure 2. Functional Block Diagram
PanelLink TMDS Digital Core
The PanelLink TMDS core encodes video information onto three TMDS differential data lines and the differential
clock. The video data is input by the Data Capture Logic Block, as a 12- or 24-bit bus, using one or two clocks with
one or two edges per clock. An attached monitor may be sensed using the HTPLG pin or internally with Receiver
Sense. This detected state may be output onto the MSEN pin. The device may be powered down using the PD#
pin or with an internal register. The
SiI 164
is reset using the ISEL/RST# pin
.
A resistor tied to the EXT_SWING
pin is used to control the TMDS swing amplitude.
I
2
C Interface and Registers
The
SiI
164 uses a slave I
2
C interface, capable of running at 100kHz. The slave I
2
C interface is not 5V tolerant. If
the switching levels from the host are not 3.3V, then a voltage level shifter must be used. See Figure 16 and
Figure 17 on page 24 for a system diagram.
A connected display may be detected using the DVI Hot Plug signal, attached to the HTPLG pin; or with the
Receiver Sense logic internal to the
SiI
164
.
The state of the detection, or an interrupt signal indicating a change of
state, may be sent to the MSEN pin. This is useful to the host controller monitoring the
SiI
164
.
Summary of Contents for DV985S
Page 1: ...SERVICE MANUAL DV985S...
Page 6: ...5 1 Optical pickup Unit Explosed View and Part List Pic 1...
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