BBK DV985S Service Manual Download

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SiI

164

PanelLink

Transmitter

Data Sheet

Pin Descriptions (cont’d)

Configuration Pins

Pin Name Pin # Type Description

MSEN 11

Out

Monitor Sense. This pin is an open collector output. The behavior of this output depends on
whether I

C interface active:

C bus inactive (ISEL/RST# = LOW)

HIGH level indicates a powered on receiver is detected at the differential outputs.

A LOW level indicates a powered on receiver is not detected.

C bus is enabled (ISEL/RST# = HIGH)

The output is programmable through the I

C interface (see I

C Register Definitions).

An external 5K pull-up resistor to VDDQ is required on this pin.

ISEL/RST# 13 In I

C Interface Select.

ISEL/RST#=HIGH

C interface is active.

ISEL/RST#=LOW

C is inactive and the chip configuration is read from the configuration strapping pins. This pin

also acts as an asynchronous reset to the I

C interface controller. The reset is active when this

input is held LOW.

Note

: When the I

C interface is active, DKEN must be set HIGH.

BSEL/SCL 15 In Input bus select / I

C clock. This pin is an open collector input. If I

C bus is enabled

(ISEL/RST# = HIGH), then this pin is the I

C clock input. If the I

C is disabled (ISEL/RST# =

LOW), then this pin selects the input bus width.

Input Bus Select:

HIGH selects 24-bit input mode
LOW selects 12-bit input mode

DSEL/SDA 14 In/Out

Dual edge clock select / I

C Data. This pin is an open collector input/output. If I

C bus is

enabled (ISEL/RST# = HIGH), then this pin is the I

C data line. If the I

C bus is disabled

(ISEL/RST# = LOW), then this pin selects whether single clock dual edge is used.

Dual Edge clock select:

When HIGH, IDCK+ latches input data on both falling and rising clock edges.
When LOW, IDCK+/IDCK- latches input data on only falling or rising clock edges.

In 24-/12-bit mode:

If HIGH (dual edge), IDCK+ is used to latch data on both falling and rising edges.
If LOW (single edge), IDCK+ latches 1

half data and IDCK- latches 2

half data.

EDGE/

HTPLG

9 In

Edge select / Hot Plug input. If the I

C bus is enabled (ISEL/RST# = HIGH), then this pin is

used to monitor the “Hot Plug” detect signal (Please refer to the DVI

or VESA

P&D

and

DFP standards). This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit.
If I

C bus is disabled (ISEL/RST# = LOW), then this pin selects the clock edge that will latch

the data. How the EDGE setting works depends on whether dual or single edge latching is
selected:

Dual Edge Mode (DSEL = HIGH)

EDGE = LOW, the primary edge (first latch edge after DE is asserted) is the falling edge.
EDGE = HIGH, the primary edge (first latch edge after DE is asserted) is the rising edge.

Note:

In 24-bit Single Clock Dual Edge mode, EDGE is ignored.

Single Edge Mode (DSEL = LOW)

EDGE = LOW, the falling edge of the clock is used to latch data.
EDGE = HIGH, the rising edge of the clock is used to latch data.

DKEN 35 In

De-skewing enable.

C mode (ISEL/RST# = HIGH)

DKEN pin must be set to HIGH. DK[3:1] pins are ignored and the De-skewing increments are
selected through the I

C interface (see the I

C register definitions).

Non I

C mode (ISEL/RST# = LOW)