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CXD3068Q
[4] Description of other functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T.
In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that
is the channel clock, is necessary.
In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD3068Q has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when
not using the internal VCO2, external LPF and VCO are necessary.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the
secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency
components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields
better playability. However, in this case the capture range becomes
±
50kHz.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
Summary of Contents for PV420S
Page 1: ...SERVICE MANUAL PV420S WWW BBK RU ...
Page 72: ... 69 CXD3068Q Block Diagram ...
Page 73: ... 70 CXD3068Q Pin Configuration ...
Page 122: ... 119 CXD3068Q Timing Chart 1 3 ...
Page 123: ... 120 CXD3068Q Timing Chart 1 4 ...
Page 124: ... 121 CXD3068Q Timing Chart 1 5 ...
Page 129: ... 126 CXD3068Q Timing Chart 2 1 ...
Page 130: ... 127 CXD3068Q Block Diagram 2 2 ...
Page 131: ... 128 CXD3068Q Timing Chart 2 3 ...
Page 134: ... 131 CXD3068Q Timing Chart 2 6 ...
Page 138: ... 135 CXD3068Q VCO C Mode Fig 3 3 Access Flow Chart Using VCO Control ...
Page 140: ... 137 CXD3068Q Block Diagram 4 1 ...
Page 143: ... 140 CXD3068Q Timing Chart 4 4 ...
Page 147: ... 144 CXD3068Q Fig 4 6 a Auto Focus Flow Chart Fig 4 6 b Auto Focus Timing Chart ...
Page 148: ... 145 CXD3068Q Fig 4 7 a 1 Track Jump Flow Chart Fig 4 7 b 1 Track Jump Timing Chart ...
Page 149: ... 146 CXD3068Q Fig 4 8 a 10 Track Jump Flow Chart Fig 4 8 b 10 Track Jump Timing Chart ...
Page 150: ... 147 CXD3068Q Fig 4 9 a 2N Track Jump Flow Chart Fig 4 9 b 2N Track Jump Timing Chart ...
Page 151: ... 148 CXD3068Q Fig 4 10 a Fine Search Flow Chart Fig 4 10 b Fine Search Timing Chart ...
Page 152: ... 149 CXD3068Q Fig 4 11 a M Track Move Flow Chart Fig 4 11 b M Track Move Timing Chart ...
Page 157: ... 154 CXD3068Q Fig 4 15 CD TEXT Data Timing Chart ...
Page 162: ... 159 CXD3068Q Fig 5 3a Fig 5 3b ...
Page 196: ... 193 CXD3068Q Description of Data Readout ...
Page 200: ... 197 CXD3068Q ...
Page 201: ... 198 CXD3068Q ...
Page 202: ... 199 CXD3068Q ...
Page 207: ... 204 CXD3068Q Package Outline Unit mm ...
Page 208: ...This data sheet has been made from recycled paper to help protect the environment 205 ...
