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SPCA717A
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
235 NOV. 11, 2002
Preliminary Version: 0.1
6.FUNCTIONAL DESCRIPTIONS
6.1. Mode Selection
Master mode is selected when MASTER = 1; slave mode is
selected when MASTER = 0. Two pins, MODEA, MODEB, drive
three different configuration registers. The most common operating
modes can be selected with these pins while in master mode. In
slave mode, the common operating modes are automatically
determined from the timing of the incoming HSYNC* and VSYNC*
signals.
Note:
The term “common operating mode” refers to North American NTSC and
Western European PAL
Table 1
illustrates the multi-functionality of the
mode pins during master and slave mode. To access the more exotic
video formats, slave mode is preferred since the necessary registers are
always accessible. If master mode is needed, the less common modes
can still be programmed by first registering the modes as a slave, and then
switching to a master. During power-up, the MODEA and MODEB pins
configure the master registers; i.e., EFIELD, PAL625, are written. Also,
during power-up, the slave registers are reset to zero, i.e., YCSWAP.
Table 1.
Mode Selection
PIN Description
The MASTER pin
MODEA
MODEB
0
YCSWAP
PALSA
1
EFIELD
PAL625
Table 2.
Configuration Register Settings
Mode Register Name
Set to 0
Set to 1
Comments
EFIELD
The VSYNC pin will output normal
vertical synchronization signal.
The VSYNC pin will output field signal.
Low at VSYNC pin for even field, high
for odd field
This is only used at master
mode.
PAL625
525-line operation will be select
The 625-line operation will be select
This is only used at master
mode
YCSWAP
Do not swap Y and Cr/Cb
Swap Y and Cr/Cb sequence
-
PALSA
When PAL625 register is set to high,
PAL-BDGHI mode is selected. When
PAL625 register is set to low, NTSC
mode is selected.
When PAL625 register is set to high,
PAL-Nc mode is selected. When
PAL625 register is set to low, PAL-M
mode is selected.
-
6.2. Clock Timing
A clock signal with a frequency twice the luminance sampling rate
must be present at the CLK pin. All setup and hold timing
specifications are measured with respect to the rising edge of this
signal.
6.3. Pixel Input Timing
6.3.1. Pixel sequence
Multiplexed Y, Cb, and Cr data is input through the DATA[7:0]
inputs. By default, the input sequence for active video pixels
must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance
with CCIR-656. This pattern begins during the first CLK period
after the falling edge of HSYNC* (regardless of the setting of
SLAVE/MASTER mode). The order of Cb and Cr can be
reversed by setting the CBSWAP pin.
Figure 1
illustrates the
timing. If the pixel stream input to the SPCA717A is off by one
CLK period, the SPCA717A can lock to the pixel stream by setting
the YCSWAP register. This would solve the problem of having
the Y and Cr/Cb pixels swapped.
Summary of Contents for PV420S
Page 1: ...SERVICE MANUAL PV420S WWW BBK RU ...
Page 72: ... 69 CXD3068Q Block Diagram ...
Page 73: ... 70 CXD3068Q Pin Configuration ...
Page 122: ... 119 CXD3068Q Timing Chart 1 3 ...
Page 123: ... 120 CXD3068Q Timing Chart 1 4 ...
Page 124: ... 121 CXD3068Q Timing Chart 1 5 ...
Page 129: ... 126 CXD3068Q Timing Chart 2 1 ...
Page 130: ... 127 CXD3068Q Block Diagram 2 2 ...
Page 131: ... 128 CXD3068Q Timing Chart 2 3 ...
Page 134: ... 131 CXD3068Q Timing Chart 2 6 ...
Page 138: ... 135 CXD3068Q VCO C Mode Fig 3 3 Access Flow Chart Using VCO Control ...
Page 140: ... 137 CXD3068Q Block Diagram 4 1 ...
Page 143: ... 140 CXD3068Q Timing Chart 4 4 ...
Page 147: ... 144 CXD3068Q Fig 4 6 a Auto Focus Flow Chart Fig 4 6 b Auto Focus Timing Chart ...
Page 148: ... 145 CXD3068Q Fig 4 7 a 1 Track Jump Flow Chart Fig 4 7 b 1 Track Jump Timing Chart ...
Page 149: ... 146 CXD3068Q Fig 4 8 a 10 Track Jump Flow Chart Fig 4 8 b 10 Track Jump Timing Chart ...
Page 150: ... 147 CXD3068Q Fig 4 9 a 2N Track Jump Flow Chart Fig 4 9 b 2N Track Jump Timing Chart ...
Page 151: ... 148 CXD3068Q Fig 4 10 a Fine Search Flow Chart Fig 4 10 b Fine Search Timing Chart ...
Page 152: ... 149 CXD3068Q Fig 4 11 a M Track Move Flow Chart Fig 4 11 b M Track Move Timing Chart ...
Page 157: ... 154 CXD3068Q Fig 4 15 CD TEXT Data Timing Chart ...
Page 162: ... 159 CXD3068Q Fig 5 3a Fig 5 3b ...
Page 196: ... 193 CXD3068Q Description of Data Readout ...
Page 200: ... 197 CXD3068Q ...
Page 201: ... 198 CXD3068Q ...
Page 202: ... 199 CXD3068Q ...
Page 207: ... 204 CXD3068Q Package Outline Unit mm ...
Page 208: ...This data sheet has been made from recycled paper to help protect the environment 205 ...
