P
P
r
r
e
e
l
l
i
i
m
m
i
i
n
n
a
a
r
r
y
y
SPCA717A
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
244 NOV. 11, 2002
Preliminary Version: 0.1
8.APPLICATION CIRCUITS
8.1. PC Board Considerations
The layout should be optimized for lowest noise on the power and
ground planes by providing good decoupling. The trace length
between groups of VAA and GND pins should be as short as
possible to minimize inductive ringing. A well-designed power
distribution network is critical to eliminate digital switching noise.
The ground plane must provide a low -impedance return path for
the digital circuits. A PC board with a minimum of four layers is
recommended, with layers 1 (top) and 4 (bottom) for signals and
layers 2 and 3 for ground and power, respectively.
8.2. Component Placement
Components should be placed as close as possible to the
associated pin. The optimum layout enables the SPCA717A to
be located as close as possible to the power supply connector and
the video output connector.
8.3. Power And Ground Planes
For optimum performance, a common digital and analog ground
plane is recommended. Separate digital and analog power
planes are recommended. The digital power plane should
provide power to all digital logic on the PC board, and the analog
power plane should provide power to all SPCA717A power pins,
VREF circuitry, and COMP decoupling. At least a 1/8-inch gap is
required in between the digital power plane and the analog power
plane. The analog power plane should be connected to the
digital power plane (VCC) at a single point through a ferrite bead,
as illustrated in
Figure 4, Table 6.
This bead should be located
within 3 inches of the SPCA717A. The bead provides resistance
to switching-currents, acting as a resistance at high frequencies.
A low -resistance bead should be used, such as Ferroxcube
5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.
Figure 4.
Typical Connection Diagram (Internal Voltage Reference)
Note1:
Some modulators may require AC coupling capacitors (10
µ
F).
Note2:
Optional for chroma boost.
Note3:
VREF IN must be connected to either VREFOUT or VBIAS.
Summary of Contents for PV420S
Page 1: ...SERVICE MANUAL PV420S WWW BBK RU ...
Page 72: ... 69 CXD3068Q Block Diagram ...
Page 73: ... 70 CXD3068Q Pin Configuration ...
Page 122: ... 119 CXD3068Q Timing Chart 1 3 ...
Page 123: ... 120 CXD3068Q Timing Chart 1 4 ...
Page 124: ... 121 CXD3068Q Timing Chart 1 5 ...
Page 129: ... 126 CXD3068Q Timing Chart 2 1 ...
Page 130: ... 127 CXD3068Q Block Diagram 2 2 ...
Page 131: ... 128 CXD3068Q Timing Chart 2 3 ...
Page 134: ... 131 CXD3068Q Timing Chart 2 6 ...
Page 138: ... 135 CXD3068Q VCO C Mode Fig 3 3 Access Flow Chart Using VCO Control ...
Page 140: ... 137 CXD3068Q Block Diagram 4 1 ...
Page 143: ... 140 CXD3068Q Timing Chart 4 4 ...
Page 147: ... 144 CXD3068Q Fig 4 6 a Auto Focus Flow Chart Fig 4 6 b Auto Focus Timing Chart ...
Page 148: ... 145 CXD3068Q Fig 4 7 a 1 Track Jump Flow Chart Fig 4 7 b 1 Track Jump Timing Chart ...
Page 149: ... 146 CXD3068Q Fig 4 8 a 10 Track Jump Flow Chart Fig 4 8 b 10 Track Jump Timing Chart ...
Page 150: ... 147 CXD3068Q Fig 4 9 a 2N Track Jump Flow Chart Fig 4 9 b 2N Track Jump Timing Chart ...
Page 151: ... 148 CXD3068Q Fig 4 10 a Fine Search Flow Chart Fig 4 10 b Fine Search Timing Chart ...
Page 152: ... 149 CXD3068Q Fig 4 11 a M Track Move Flow Chart Fig 4 11 b M Track Move Timing Chart ...
Page 157: ... 154 CXD3068Q Fig 4 15 CD TEXT Data Timing Chart ...
Page 162: ... 159 CXD3068Q Fig 5 3a Fig 5 3b ...
Page 196: ... 193 CXD3068Q Description of Data Readout ...
Page 200: ... 197 CXD3068Q ...
Page 201: ... 198 CXD3068Q ...
Page 202: ... 199 CXD3068Q ...
Page 207: ... 204 CXD3068Q Package Outline Unit mm ...
Page 208: ...This data sheet has been made from recycled paper to help protect the environment 205 ...
